uart_if.vo

this is a sample about UART transmission,it s default installation is D:RedLogicRCII_samples, and th

	.datab(\inst2|cnt[3] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(\inst2|cnt[2]~165 ),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst2|cnt[3] ),
	.cout(),
	.cout0(\inst2|cnt[3]~161 ),
	.cout1(\inst2|cnt[3]~161COUT1_194 ));
// synopsys translate_off
defparam \inst2|cnt[3]~I .operation_mode = "arithmetic";
defparam \inst2|cnt[3]~I .synch_mode = "off";
defparam \inst2|cnt[3]~I .register_cascade_mode = "off";
defparam \inst2|cnt[3]~I .sum_lutc_input = "cin";
defparam \inst2|cnt[3]~I .lut_mask = "3C3F";
defparam \inst2|cnt[3]~I .cin_used = "true";
defparam \inst2|cnt[3]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X9_Y14_N4
cyclone_lcell \inst2|cnt[2]~I (
// Equation(s):
// \inst2|cnt[2]  = DFFEAS(\inst2|cnt[2]  $ !\inst2|cnt[1]~169 , GLOBAL(\inst5|acc[12] ), VCC, , , , , , )
// \inst2|cnt[2]~165  = CARRY(\inst2|cnt[2]  & !\inst2|cnt[1]~169COUT1_192 )

	.clk(\inst5|acc[12] ),
	.dataa(vcc),
	.datab(\inst2|cnt[2] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\inst2|cnt[1]~169 ),
	.cin1(\inst2|cnt[1]~169COUT1_192 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst2|cnt[2] ),
	.cout(\inst2|cnt[2]~165 ),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst2|cnt[2]~I .operation_mode = "arithmetic";
defparam \inst2|cnt[2]~I .synch_mode = "off";
defparam \inst2|cnt[2]~I .register_cascade_mode = "off";
defparam \inst2|cnt[2]~I .sum_lutc_input = "cin";
defparam \inst2|cnt[2]~I .lut_mask = "C30C";
defparam \inst2|cnt[2]~I .cin0_used = "true";
defparam \inst2|cnt[2]~I .cin1_used = "true";
defparam \inst2|cnt[2]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X9_Y14_N3
cyclone_lcell \inst2|cnt[1]~I (
// Equation(s):
// \inst2|cnt[1]  = DFFEAS(\inst2|cnt[1]  $ \inst2|cnt[0]~173 , GLOBAL(\inst5|acc[12] ), VCC, , , , , , )
// \inst2|cnt[1]~169  = CARRY(!\inst2|cnt[0]~173  # !\inst2|cnt[1] )
// \inst2|cnt[1]~169COUT1_192  = CARRY(!\inst2|cnt[0]~173COUT1_190  # !\inst2|cnt[1] )

	.clk(\inst5|acc[12] ),
	.dataa(vcc),
	.datab(\inst2|cnt[1] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\inst2|cnt[0]~173 ),
	.cin1(\inst2|cnt[0]~173COUT1_190 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst2|cnt[1] ),
	.cout(),
	.cout0(\inst2|cnt[1]~169 ),
	.cout1(\inst2|cnt[1]~169COUT1_192 ));
// synopsys translate_off
defparam \inst2|cnt[1]~I .operation_mode = "arithmetic";
defparam \inst2|cnt[1]~I .synch_mode = "off";
defparam \inst2|cnt[1]~I .register_cascade_mode = "off";
defparam \inst2|cnt[1]~I .sum_lutc_input = "cin";
defparam \inst2|cnt[1]~I .lut_mask = "3C3F";
defparam \inst2|cnt[1]~I .cin0_used = "true";
defparam \inst2|cnt[1]~I .cin1_used = "true";
defparam \inst2|cnt[1]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X9_Y14_N2
cyclone_lcell \inst2|cnt[0]~I (
// Equation(s):
// \inst2|cnt[0]  = DFFEAS(!\inst2|cnt[0] , GLOBAL(\inst5|acc[12] ), VCC, , , , , , )
// \inst2|cnt[0]~173  = CARRY(\inst2|cnt[0] )
// \inst2|cnt[0]~173COUT1_190  = CARRY(\inst2|cnt[0] )

	.clk(\inst5|acc[12] ),
	.dataa(\inst2|cnt[0] ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst2|cnt[0] ),
	.cout(),
	.cout0(\inst2|cnt[0]~173 ),
	.cout1(\inst2|cnt[0]~173COUT1_190 ));
// synopsys translate_off
defparam \inst2|cnt[0]~I .operation_mode = "arithmetic";
defparam \inst2|cnt[0]~I .synch_mode = "off";
defparam \inst2|cnt[0]~I .register_cascade_mode = "off";
defparam \inst2|cnt[0]~I .sum_lutc_input = "datac";
defparam \inst2|cnt[0]~I .lut_mask = "55AA";
defparam \inst2|cnt[0]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at PIN_131
cyclone_io \rst_n~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rst_n~combout ),
	.regout(),
	.padio(rst_n));
// synopsys translate_off
defparam \rst_n~I .operation_mode = "input";
defparam \rst_n~I .input_register_mode = "none";
defparam \rst_n~I .output_register_mode = "none";
defparam \rst_n~I .oe_register_mode = "none";
defparam \rst_n~I .input_async_reset = "none";
defparam \rst_n~I .output_async_reset = "none";
defparam \rst_n~I .oe_async_reset = "none";
defparam \rst_n~I .input_sync_reset = "none";
defparam \rst_n~I .output_sync_reset = "none";
defparam \rst_n~I .oe_sync_reset = "none";
defparam \rst_n~I .input_power_up = "low";
defparam \rst_n~I .output_power_up = "low";
defparam \rst_n~I .oe_power_up = "low";
// synopsys translate_on

// atom is at LC_X9_Y13_N9
cyclone_lcell \inst2|rst_out~I (
// Equation(s):
// \inst|U1|u2|N_383_i  = !D1_rst_out # !\inst|U1|u2|clk1x_enable 
// \inst2|rst_out  = DFFEAS(\inst|U1|u2|N_383_i , \inst2|cnt[15] , VCC, , , \rst_n~combout , , , VCC)

	.clk(\inst2|cnt[15] ),
	.dataa(vcc),
	.datab(\inst|U1|u2|clk1x_enable ),
	.datac(\rst_n~combout ),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst|U1|u2|N_383_i ),
	.regout(\inst2|rst_out ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst2|rst_out~I .operation_mode = "normal";
defparam \inst2|rst_out~I .synch_mode = "on";
defparam \inst2|rst_out~I .register_cascade_mode = "off";
defparam \inst2|rst_out~I .sum_lutc_input = "qfbk";
defparam \inst2|rst_out~I .lut_mask = "3F3F";
defparam \inst2|rst_out~I .output_mode = "reg_and_comb";
// synopsys translate_on

// atom is at LC_X14_Y13_N8
cyclone_lcell \inst|U1|u2|no_bits_sent_0_ (
// Equation(s):
// \inst|U1|u2|no_bits_sent_0  = DFFEAS(!\inst|U1|u2|no_bits_sent_0 , GLOBAL(\inst|U1|u2|U1_u2_clkdiv[3] ), !\inst|U1|u2|N_383_i , , , , , , )

	.clk(\inst|U1|u2|U1_u2_clkdiv[3] ),
	.dataa(vcc),
	.datab(vcc),
	.datac(\inst|U1|u2|no_bits_sent_0 ),
	.datad(vcc),
	.aclr(\inst|U1|u2|N_383_i ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst|U1|u2|no_bits_sent_0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst|U1|u2|no_bits_sent_0_ .operation_mode = "normal";
defparam \inst|U1|u2|no_bits_sent_0_ .synch_mode = "off";
defparam \inst|U1|u2|no_bits_sent_0_ .register_cascade_mode = "off";
defparam \inst|U1|u2|no_bits_sent_0_ .sum_lutc_input = "datac";
defparam \inst|U1|u2|no_bits_sent_0_ .lut_mask = "0F0F";
defparam \inst|U1|u2|no_bits_sent_0_ .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X14_Y13_N9
cyclone_lcell \inst|U1|u2|no_bits_sent_1_ (
// Equation(s):
// \inst|U1|u2|no_bits_sent_1  = DFFEAS(\inst|U1|u2|no_bits_sent_1  $ (\inst|U1|u2|no_bits_sent_0 ), GLOBAL(\inst|U1|u2|U1_u2_clkdiv[3] ), !\inst|U1|u2|N_383_i , , , , , , )

	.clk(\inst|U1|u2|U1_u2_clkdiv[3] ),
	.dataa(\inst|U1|u2|no_bits_sent_1 ),
	.datab(vcc),
	.datac(\inst|U1|u2|no_bits_sent_0 ),
	.datad(vcc),
	.aclr(\inst|U1|u2|N_383_i ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst|U1|u2|no_bits_sent_1 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst|U1|u2|no_bits_sent_1_ .operation_mode = "normal";
defparam \inst|U1|u2|no_bits_sent_1_ .synch_mode = "off";
defparam \inst|U1|u2|no_bits_sent_1_ .register_cascade_mode = "off";
defparam \inst|U1|u2|no_bits_sent_1_ .sum_lutc_input = "datac";
defparam \inst|U1|u2|no_bits_sent_1_ .lut_mask = "5A5A";
defparam \inst|U1|u2|no_bits_sent_1_ .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X14_Y13_N7
cyclone_lcell \inst|U1|u2|no_bits_sent_2_ (
// Equation(s):
// \inst|U1|u2|no_bits_sent_2  = DFFEAS(\inst|U1|u2|no_bits_sent_2  $ (\inst|U1|u2|no_bits_sent_1  & \inst|U1|u2|no_bits_sent_0 ), GLOBAL(\inst|U1|u2|U1_u2_clkdiv[3] ), !\inst|U1|u2|N_383_i , , , , , , )

	.clk(\inst|U1|u2|U1_u2_clkdiv[3] ),
	.dataa(\inst|U1|u2|no_bits_sent_1 ),
	.datab(\inst|U1|u2|no_bits_sent_0 ),
	.datac(\inst|U1|u2|no_bits_sent_2 ),
	.datad(vcc),
	.aclr(\inst|U1|u2|N_383_i ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst|U1|u2|no_bits_sent_2 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst|U1|u2|no_bits_sent_2_ .operation_mode = "normal";
defparam \inst|U1|u2|no_bits_sent_2_ .synch_mode = "off";
defparam \inst|U1|u2|no_bits_sent_2_ .register_cascade_mode = "off";
defparam \inst|U1|u2|no_bits_sent_2_ .sum_lutc_input = "datac";
defparam \inst|U1|u2|no_bits_sent_2_ .lut_mask = "7878";
defparam \inst|U1|u2|no_bits_sent_2_ .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X14_Y13_N3
cyclone_lcell \inst|U1|u2|no_bits_sent_3_ (
// Equation(s):
// \inst|U1|u2|no_bits_sent_3  = DFFEAS(\inst|U1|u2|no_bits_sent_3  $ (\inst|U1|u2|no_bits_sent_2  & \inst|U1|u2|no_bits_sent_1  & \inst|U1|u2|no_bits_sent_0 ), GLOBAL(\inst|U1|u2|U1_u2_clkdiv[3] ), !\inst|U1|u2|N_383_i , , , , , , )

	.clk(\inst|U1|u2|U1_u2_clkdiv[3] ),
	.dataa(\inst|U1|u2|no_bits_sent_2 ),
	.datab(\inst|U1|u2|no_bits_sent_3 ),
	.datac(\inst|U1|u2|no_bits_sent_1 ),
	.datad(\inst|U1|u2|no_bits_sent_0 ),
	.aclr(\inst|U1|u2|N_383_i ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst|U1|u2|no_bits_sent_3 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst|U1|u2|no_bits_sent_3_ .operation_mode = "normal";
defparam \inst|U1|u2|no_bits_sent_3_ .synch_mode = "off";
defparam \inst|U1|u2|no_bits_sent_3_ .register_cascade_mode = "off";
defparam \inst|U1|u2|no_bits_sent_3_ .sum_lutc_input = "datac";
defparam \inst|U1|u2|no_bits_sent_3_ .lut_mask = "6CCC";
defparam \inst|U1|u2|no_bits_sent_3_ .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X10_Y13_N6
cyclone_lcell \inst|U1|u2|un17_clk1x_enable_a_Z (
// Equation(s):
// \inst|U1|u2|un17_clk1x_enable_a  = !\inst|U1|u2|no_bits_sent_1  & \inst|U1|u2|no_bits_sent_0  & \inst|U1|u2|no_bits_sent_2 

	.clk(gnd),
	.dataa(vcc),
	.datab(\inst|U1|u2|no_bits_sent_1 ),
	.datac(\inst|U1|u2|no_bits_sent_0 ),
	.datad(\inst|U1|u2|no_bits_sent_2 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst|U1|u2|un17_clk1x_enable_a ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst|U1|u2|un17_clk1x_enable_a_Z .operation_mode = "normal";
defparam \inst|U1|u2|un17_clk1x_enable_a_Z .synch_mode = "off";
defparam \inst|U1|u2|un17_clk1x_enable_a_Z .register_cascade_mode = "off";
defparam \inst|U1|u2|un17_clk1x_enable_a_Z .sum_lutc_input = "datac";
defparam \inst|U1|u2|un17_clk1x_enable_a_Z .lut_mask = "3000";
defparam \inst|U1|u2|un17_clk1x_enable_a_Z .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC_X10_Y13_N7
cyclone_lcell \inst|U1|u2|wrn2_i_Z (
// Equation(s):
// \inst|U1|u2|un17_clk1x_enable  = \inst|U1|u2|no_bits_sent_3  & (\inst|U1|u2|un17_clk1x_enable_a  # \inst|U1|u2|wrn1_i_0  & !H1_wrn2_i) # !\inst|U1|u2|no_bits_sent_3  & \inst|U1|u2|wrn1_i_0  & !H1_wrn2_i
// \inst|U1|u2|wrn2_i  = DFFEAS(\inst|U1|u2|un17_clk1x_enable , GLOBAL(\inst5|acc[12] ), GLOBAL(\inst2|rst_out ), , , \inst|U1|u2|wrn1_i_0 , , , VCC)

	.clk(\inst5|acc[12] ),
	.dataa(\inst|U1|u2|no_bits_sent_3 ),
	.datab(\inst|U1|u2|wrn1_i_0 ),
	.datac(\inst|U1|u2|wrn1_i_0 ),
	.datad(\inst|U1|u2|un17_clk1x_enable_a ),
	.aclr(!\inst2|rst_out ),
	.aload(gnd),
	.sclr(gnd),
	.sload(vcc),
	.ena(vcc),
	.cin(gnd),
	.cin0