uart_if.vo

this is a sample about UART transmission,it s default installation is D:RedLogicRCII_samples, and th

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 5.0 Build 148 04/26/2005 SJ Full Version"

// DATE "08/29/2007 17:06:01"

// 
// Device: Altera EP1C12Q240C8 Package PQFP240
// 

// 
// This Verilog file should be used for ModelSim (Verilog HDL output from Quartus II) only
// 

`timescale 1 ps/ 1 ps

module 	uart_if_rom (
	rst_n,
	MCLK,
	rxd,
	txd);
input 	rst_n;
input 	MCLK;
input 	rxd;
output 	txd;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("uart_if_v.sdo");
// synopsys translate_on

wire \inst5|acc[12] ;
wire \inst2|cnt[15] ;
wire \inst5|acc[11]~96 ;
wire \inst5|acc[11]~96COUT1_170 ;
wire \inst5|acc[11] ;
wire \inst2|cnt[14]~117 ;
wire \inst2|cnt[14]~117COUT1_212 ;
wire \inst2|cnt[14] ;
wire \inst5|acc[10]~100 ;
wire \inst5|acc[10] ;
wire \inst2|cnt[13]~121 ;
wire \inst2|cnt[13]~121COUT1_210 ;
wire \inst2|cnt[13] ;
wire \inst5|acc[9]~104 ;
wire \inst5|acc[9]~104COUT1_168 ;
wire \inst5|acc[9] ;
wire \inst|cnt[3] ;
wire \inst2|cnt[12]~125 ;
wire \inst2|cnt[12] ;
wire \inst5|acc[8]~108 ;
wire \inst5|acc[8]~108COUT1_166 ;
wire \inst5|acc[8] ;
wire \inst|cnt[0] ;
wire \inst|cnt[1] ;
wire \inst|cnt[2] ;
wire \inst|U1|u1|rbr_0_ ;
wire \inst2|cnt[11]~129 ;
wire \inst2|cnt[11]~129COUT1_208 ;
wire \inst2|cnt[11] ;
wire \inst5|acc[7]~112 ;
wire \inst5|acc[7]~112COUT1_164 ;
wire \inst5|acc[7] ;
wire \inst|U1|u1|U1_u1_clkdiv[3] ;
wire \inst|U1|u1|rbr_4_ ;
wire \inst2|cnt[10]~133 ;
wire \inst2|cnt[10]~133COUT1_206 ;
wire \inst2|cnt[10] ;
wire \inst5|acc[6]~116 ;
wire \inst5|acc[6]~116COUT1_162 ;
wire \inst5|acc[6] ;
wire \inst|U1|u1|clkdiv[2] ;
wire \inst|U1|u1|clkdiv[1] ;
wire \inst|U1|u1|clkdiv_5_sum3_a ;
wire \inst2|cnt[9]~137 ;
wire \inst2|cnt[9]~137COUT1_204 ;
wire \inst2|cnt[9] ;
wire \inst5|acc[5]~120 ;
wire \inst5|acc[5] ;
wire \inst|U1|u1|clk1x_enable ;
wire \inst|U1|u1|clkdiv[0] ;
wire \inst2|cnt[8]~141 ;
wire \inst2|cnt[8]~141COUT1_202 ;
wire \inst2|cnt[8] ;
wire \inst5|acc[4]~124 ;
wire \inst5|acc[4]~124COUT1_160 ;
wire \inst5|acc[4] ;
wire \inst2|cnt[7]~145 ;
wire \inst2|cnt[7] ;
wire \inst5|acc[3]~128 ;
wire \inst5|acc[3]~128COUT1_158 ;
wire \inst5|acc[3] ;
wire \inst2|cnt[6]~149 ;
wire \inst2|cnt[6]~149COUT1_200 ;
wire \inst2|cnt[6] ;
wire \inst5|acc[2]~132 ;
wire \inst5|acc[2]~132COUT1_156 ;
wire \inst5|acc[2] ;
wire \inst2|cnt[5]~153 ;
wire \inst2|cnt[5]~153COUT1_198 ;
wire \inst2|cnt[5] ;
wire \inst5|acc[1]~136 ;
wire \inst5|acc[1]~136COUT1_154 ;
wire \inst5|acc[1] ;
wire \inst2|cnt[4]~157 ;
wire \inst2|cnt[4]~157COUT1_196 ;
wire \inst2|cnt[4] ;
wire \inst5|acc[0]~140 ;
wire \inst5|acc[0] ;
wire \inst2|cnt[3]~161 ;
wire \inst2|cnt[3]~161COUT1_194 ;
wire \inst2|cnt[3] ;
wire \inst2|cnt[2]~165 ;
wire \inst2|cnt[2] ;
wire \inst2|cnt[1]~169 ;
wire \inst2|cnt[1]~169COUT1_192 ;
wire \inst2|cnt[1] ;
wire \inst2|cnt[0]~173 ;
wire \inst2|cnt[0]~173COUT1_190 ;
wire \inst2|cnt[0] ;
wire \rst_n~combout ;
wire \inst|U1|u2|N_383_i ;
wire \inst|U1|u2|no_bits_sent_0 ;
wire \inst|U1|u2|no_bits_sent_1 ;
wire \inst|U1|u2|no_bits_sent_2 ;
wire \inst|U1|u2|no_bits_sent_3 ;
wire \inst|U1|u2|un17_clk1x_enable_a ;
wire \inst2|rst_out ;
wire \inst|U1|u2|wrn2_i ;
wire \inst|U1|u2|un17_clk1x_enable ;
wire \inst|U1|u2|clk1x_enable13 ;
wire \inst|U1|u2|un1_clk1x_enable13_2_a ;
wire \inst|U1|u2|un1_clk1x_enable13_2_i ;
wire \inst|U1|u2|tbre ;
wire \~GND ;
wire \rxd~combout ;
wire \inst|U1|u1|rxd1_i_0 ;
wire \inst|U1|u1|no_bits_rcvd[1] ;
wire \inst|U1|u1|no_bits_rcvd[2] ;
wire \inst|U1|u1|N_396_i ;
wire \inst|U1|u1|clk1x_enable_0 ;
wire \inst|U1|u1|no_bits_rcvd[0] ;
wire \inst|U1|u1|no_bits_rcvd[3] ;
wire \inst|U1|u1|un1_clk1x_enable13_0_a ;
wire \inst|U1|u1|rxd2_i ;
wire \inst|U1|u1|parity8_0_x2 ;
wire \inst|U1|u1|rsr[7] ;
wire \inst|U1|u1|rsr[6] ;
wire \inst|U1|u1|rsr[5] ;
wire \inst|U1|u1|rsr[4] ;
wire \inst|U1|u1|rsr[3] ;
wire \inst|U1|u1|parity9_0_a3 ;
wire \inst|U1|u1|rbr_2 ;
wire \inst|U1|u1|N_96_i ;
wire \inst|U1|u1|data_ready12_0_a2 ;
wire \inst|U1|u1|data_ready ;
wire \inst|rdn_d_i_0 ;
wire \inst|rdn_d2_i ;
wire \inst|rdn_i_0 ;
wire \inst|U1|u1|rbr[6] ;
wire \inst|U1|u1|rbr[5] ;
wire \inst|U1|u1|read_en_6_0_a4_1_x ;
wire \inst|U1|u1|rbr[7] ;
wire \inst|U1|u1|rsr[2] ;
wire \inst|U1|u1|rsr[1] ;
wire \inst|U1|u1|rsr[0] ;
wire \inst|U1|u1|rbr[1] ;
wire \inst|U1|u1|read_en_6_0_a4_a ;
wire \inst|U1|u1|rbr_1 ;
wire \inst|U1|u2|tsr14 ;
wire \inst|I_39_0 ;
wire \inst|U1|u2|N_385_i ;
wire \inst|U1|u2|tsre_i ;
wire \inst|un1_rom_addr9_3_i_a ;
wire \inst|un1_rom_addr9_3_i ;
wire \inst|rom_addr_d[0] ;
wire \inst|rom_addr_d_cout[0] ;
wire \inst|rom_addr_d_cout[0]~COUT1_6 ;
wire \inst|rom_addr_d[1] ;
wire \inst|rom_addr_d_cout[1] ;
wire \inst|rom_addr_d_cout[1]~COUT1_8 ;
wire \inst|rom_addr_d[2] ;
wire \inst|rom_addr_d_cout[2] ;
wire \inst|rom_addr_d_cout[2]~COUT1_9 ;
wire \inst|rom_addr_d[3] ;
wire \inst|rom_addr_d_cout[3] ;
wire \inst|rom_addr_d[4] ;
wire \inst|rom_addr_d_cout[4] ;
wire \inst|rom_addr_d_cout[4]~COUT1_11 ;
wire \inst|rom_addr_d_cout[5] ;
wire \inst|rom_addr_d_cout[5]~COUT1_13 ;
wire \inst|rom_addr_d[6] ;
wire \inst|read_en_i_0 ;
wire \inst|N_103_i_i ;
wire \inst|rom_addrz[6] ;
wire \inst|rom_addrz[5] ;
wire \inst|rom_addrz[3] ;
wire \inst|rom_addrz[1] ;
wire \inst|rom_addrz[0] ;
wire \inst|rom_addrz[4] ;
wire \inst|rom_addrz[2] ;
wire \inst|un1_rdn_1_0_a4_a ;
wire \inst|un1_rdn_1_0_a4 ;
wire \inst|N_376_1_i ;
wire \inst|read_en_i_0_0 ;
wire \inst|rom_addr_d[5] ;
wire \inst|read_once_9_iv_i_0_a2_0_5 ;
wire \inst|read_once_9_iv_i_0_a2_0_2_a_x ;
wire \inst|read_once_9_iv_i_0_a2_0_2 ;
wire \inst|read_once ;
wire \inst|wrn_i_1 ;
wire \inst|U1|u2|wrn1_i_0 ;
wire \inst|U1|u2|clk1x_enable ;
wire \inst|U1|u2|clkdiv[0] ;
wire \inst|U1|u2|clkdiv_5_sum3_a ;
wire \inst|U1|u2|clkdiv[1] ;
wire \inst|U1|u2|clkdiv[2] ;
wire \inst|U1|u2|U1_u2_clkdiv[3] ;
wire \inst|I_43 ;
wire \MCLK~combout ;
wire \inst1|altsyncram_component|auto_generated|q_a[7] ;
wire \inst|sclrun1_rom_addr9_1_0_a2 ;
wire \inst|din[7] ;
wire \inst|U1|u2|tbr[7] ;
wire \inst|U1|u2|N_485_i ;
wire \inst|U1|u2|tsr[7] ;
wire \inst1|altsyncram_component|auto_generated|q_a[6] ;
wire \inst|din[6] ;
wire \inst|U1|u2|tbr[6] ;
wire \inst|U1|u2|tsr[6] ;
wire \inst1|altsyncram_component|auto_generated|q_a[5] ;
wire \inst|din[5] ;
wire \inst|U1|u2|tbr[5] ;
wire \inst|U1|u2|tsr[5] ;
wire \inst1|altsyncram_component|auto_generated|q_a[4] ;
wire \inst|din[4] ;
wire \inst|U1|u2|tbr[4] ;
wire \inst|U1|u2|tsr[4] ;
wire \inst1|altsyncram_component|auto_generated|q_a[3] ;
wire \inst|din[3] ;
wire \inst|U1|u2|tbr[3] ;
wire \inst|U1|u2|tsr[3] ;
wire \inst1|altsyncram_component|auto_generated|q_a[2] ;
wire \inst|din[2] ;
wire \inst|U1|u2|tbr[2] ;
wire \inst|U1|u2|tsr[2] ;
wire \inst1|altsyncram_component|auto_generated|q_a[1] ;
wire \inst|din[1] ;
wire \inst|U1|u2|tbr[1] ;
wire \inst|U1|u2|tsr[1] ;
wire \inst1|altsyncram_component|auto_generated|q_a[0] ;
wire \inst|din[0] ;
wire \inst|U1|u2|tbr[0] ;
wire \inst|U1|u2|tsr_0 ;
wire \inst|U1|u2|tsr16 ;
wire \inst|U1|u2|parity_i ;
wire \inst|I_45 ;
wire \inst|I_40_a ;
wire \inst|U1|u2|un1_tsr15_1_a_x ;
wire \inst|U1|u2|N_380_i ;
wire \inst|U1|u2|sdo_i ;

wire [7:0] \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus ;

assign \inst1|altsyncram_component|auto_generated|q_a[0]  = \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
assign \inst1|altsyncram_component|auto_generated|q_a[1]  = \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [1];
assign \inst1|altsyncram_component|auto_generated|q_a[2]  = \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [2];
assign \inst1|altsyncram_component|auto_generated|q_a[3]  = \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [3];
assign \inst1|altsyncram_component|auto_generated|q_a[4]  = \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [4];
assign \inst1|altsyncram_component|auto_generated|q_a[5]  = \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [5];
assign \inst1|altsyncram_component|auto_generated|q_a[6]  = \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [6];
assign \inst1|altsyncram_component|auto_generated|q_a[7]  = \inst1|altsyncram_component|auto_generated|ram_block1a0_PORTADATAOUT_bus [7];

// atom is at LC_X8_Y13_N6
cyclone_lcell \inst5|acc[12]~I (
// Equation(s):
// \inst5|acc[12]  = DFFEAS(!(!\inst5|acc[10]~100  & \inst5|acc[11]~96 ) # (\inst5|acc[10]~100  & \inst5|acc[11]~96COUT1_170 ), GLOBAL(\MCLK~combout ), VCC, , , , , , )

	.clk(\MCLK~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(\inst5|acc[10]~100 ),
	.cin0(\inst5|acc[11]~96 ),
	.cin1(\inst5|acc[11]~96COUT1_170 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst5|acc[12] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst5|acc[12]~I .operation_mode = "normal";
defparam \inst5|acc[12]~I .synch_mode = "off";
defparam \inst5|acc[12]~I .register_cascade_mode = "off";
defparam \inst5|acc[12]~I .sum_lutc_input = "cin";
defparam \inst5|acc[12]~I .lut_mask = "0F0F";
defparam \inst5|acc[12]~I .cin_used = "true";
defparam \inst5|acc[12]~I .cin0_used = "true";
defparam \inst5|acc[12]~I .cin1_used = "true";
defparam \inst5|acc[12]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X9_Y13_N7
cyclone_lcell \inst2|cnt[15]~I (
// Equation(s):
// \inst2|cnt[15]  = DFFEAS(\inst2|cnt[15]  $ ((!\inst2|cnt[12]~125  & \inst2|cnt[14]~117 ) # (\inst2|cnt[12]~125  & \inst2|cnt[14]~117COUT1_212 )), GLOBAL(\inst5|acc[12] ), VCC, , , , , , )

	.clk(\inst5|acc[12] ),
	.dataa(\inst2|cnt[15] ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(\inst2|cnt[12]~125 ),
	.cin0(\inst2|cnt[14]~117 ),
	.cin1(\inst2|cnt[14]~117COUT1_212 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst2|cnt[15] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst2|cnt[15]~I .operation_mode = "normal";
defparam \inst2|cnt[15]~I .synch_mode = "off";
defparam \inst2|cnt[15]~I .register_cascade_mode = "off";
defparam \inst2|cnt[15]~I .sum_lutc_input = "cin";
defparam \inst2|cnt[15]~I .lut_mask = "5A5A";
defparam \inst2|cnt[15]~I .cin_used = "true";
defparam \inst2|cnt[15]~I .cin0_used = "true";
defparam \inst2|cnt[15]~I .cin1_used = "true";
defparam \inst2|cnt[15]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X8_Y13_N5
cyclone_lcell \inst5|acc[11]~I (
// Equation(s):
// \inst5|acc[11]  = DFFEAS(\inst5|acc[11]  $ \inst5|acc[10]~100 , GLOBAL(\MCLK~combout ), VCC, , , , , , )
// \inst5|acc[11]~96  = CARRY(!\inst5|acc[10]~100  # !\inst5|acc[11] )
// \inst5|acc[11]~96COUT1_170  = CARRY(!\inst5|acc[10]~100  # !\inst5|acc[11] )

	.clk(\MCLK~combout ),
	.dataa(vcc),
	.datab(\inst5|acc[11] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(\inst5|acc[10]~100 ),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst5|acc[11] ),
	.cout(),
	.cout0(\inst5|acc[11]~96 ),
	.cout1(\inst5|acc[11]~96COUT1_170 ));
// synopsys translate_off
defparam \inst5|acc[11]~I .operation_mode = "arithmetic";
defparam \inst5|acc[11]~I .synch_mode = "off";
defparam \inst5|acc[11]~I .register_cascade_mode = "off";
defparam \inst5|acc[11]~I .sum_lutc_input = "cin";
defparam \inst5|acc[11]~I .lut_mask = "3C3F";
defparam \inst5|acc[11]~I .cin_used = "true";
defparam \inst5|acc[11]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X9_Y13_N6
cyclone_lcell \inst2|cnt[14]~I (
// Equation(s):
// \inst2|cnt[14]  = DFFEAS(\inst2|cnt[14]  $ (!(!\inst2|cnt[12]~125  & \inst2|cnt[13]~121 ) # (\inst2|cnt[12]~125  & \inst2|cnt[13]~121COUT1_210 )), GLOBAL(\inst5|acc[12] ), VCC, , , , , , )
// \inst2|cnt[14]~117  = CARRY(\inst2|cnt[14]  & (!\inst2|cnt[13]~121 ))
// \inst2|cnt[14]~117COUT1_212  = CARRY(\inst2|cnt[14]  & (!\inst2|cnt[13]~121COUT1_210 ))