uart_if_v.sdo

this is a sample about UART transmission,it s default installation is D:RedLogicRCII_samples, and th

        (PORT aclr (6517:6517:6517) (6610:6610:6610))
        (PORT clk (4260:4260:4260) (4285:4285:4285))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|U1\|u1\|no_bits_rcvd_2_.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (608:608:608) (593:593:593))
        (PORT datac (577:577:577) (591:591:591))
        (PORT datad (665:665:665) (625:625:625))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|U1\|u1\|no_bits_rcvd_2_.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (6517:6517:6517) (6610:6610:6610))
        (PORT clk (4260:4260:4260) (4285:4285:4285))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|U1\|u1\|rxd2_i_Z.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (563:563:563) (579:579:579))
        (PORT datab (649:649:649) (666:666:666))
        (PORT datac (563:563:563) (579:579:579))
        (PORT datad (727:727:727) (737:737:737))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datad regin (309:309:309) (309:309:309))
        (IOPATH qfbkin regin (613:613:613) (613:613:613))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datad combout (114:114:114) (114:114:114))
        (IOPATH qfbkin combout (378:378:378) (378:378:378))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|U1\|u1\|rxd2_i_Z.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datac (678:678:678) (694:694:694))
        (PORT aclr (4790:4790:4790) (4856:4856:4856))
        (PORT clk (4257:4257:4257) (4285:4285:4285))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
        (IOPATH (posedge clk) qfbkout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) qfbkout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (37:37:37))
      (HOLD datac (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|U1\|u1\|clk1x_enable_0_Z.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (566:566:566) (581:581:581))
        (PORT datad (1112:1112:1112) (1156:1156:1156))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|U1\|u1\|clk1x_enable_0_Z.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (4790:4790:4790) (4856:4856:4856))
        (PORT clk (4257:4257:4257) (4285:4285:4285))
        (PORT ena (1288:1288:1288) (1343:1343:1343))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|U1\|u1\|no_bits_rcvd_0_.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (653:653:653) (611:611:611))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|U1\|u1\|no_bits_rcvd_0_.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (6517:6517:6517) (6610:6610:6610))
        (PORT clk (4260:4260:4260) (4285:4285:4285))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|U1\|u1\|no_bits_rcvd_3_.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (672:672:672) (639:639:639))
        (PORT datab (557:557:557) (555:555:555))
        (PORT datac (609:609:609) (614:614:614))
        (PORT datad (635:635:635) (598:598:598))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|U1\|u1\|no_bits_rcvd_3_.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (6517:6517:6517) (6610:6610:6610))
        (PORT clk (4260:4260:4260) (4285:4285:4285))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|U1\|u1\|un1_clk1x_enable13_0_a_Z.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (657:657:657) (623:623:623))
        (PORT datac (601:601:601) (606:606:606))
        (PORT datad (650:650:650) (615:615:615))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|U1\|u1\|parity8_0_x2_Z.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (671:671:671) (638:638:638))
        (PORT datab (557:557:557) (555:555:555))
        (PORT datac (608:608:608) (610:610:610))
        (PORT datad (638:638:638) (602:602:602))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|U1\|u1\|rsr_7_.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (1577:1577:1577) (1621:1621:1621))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|U1\|u1\|rsr_7_.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (4823:4823:4823) (4890:4890:4890))
        (PORT clk (4293:4293:4293) (4319:4319:4319))
        (PORT ena (2389:2389:2389) (2477:2477:2477))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|U1\|u1\|rsr_6_.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (536:536:536) (561:561:561))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|U1\|u1\|rsr_6_.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datac (651:651:651) (676:676:676))
        (PORT aclr (4823:4823:4823) (4890:4890:4890))
        (PORT clk (4293:4293:4293) (4319:4319:4319))
        (PORT ena (2389:2389:2389) (2477:2477:2477))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datac (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|U1\|u1\|rsr_5_.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (546:546:546) (543:543:543))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|U1\|u1\|rsr_5_.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (4823:4823:4823) (4890:4890:4890))
        (PORT clk (4293:4293:4293) (4319:4319:4319))
        (PORT ena (2389:2389:2389) (2477:2477:2477))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|U1\|u1\|rsr_4_.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (538:538:538) (538:538:538))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|U1\|u1\|rsr_4_.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (4823:4823:4823) (4890:4890:4890))
        (PORT clk (4293:4293:4293) (4319:4319:4319))
        (PORT ena (2389:2389:2389) (2477:2477:2477))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|U1\|u1\|rsr_3_.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (737:737:737) (769:769:769))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|U1\|u1\|rsr_3_.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datac (852:852:852) (884:884:884))
        (PORT aclr (4823:4823:4823) (4890:4890:4890))
        (PORT clk (4293:4293:4293) (4319:4319:4319))
        (PORT ena (2394:2394:2394) (2488:2488:2488))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datac (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|U1\|u1\|parity9_0_a3_Z.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (670:670:670) (637:637:637))
        (PORT datab (557:557:557) (554:554:554))
        (PORT datac (607:607:607) (610:610:610))
        (PORT datad (641:641:641) (605:605:605))
        (IOPATH dataa combout (590:590:590) (590:590:590))
        (IOPATH datab combout (442:442:442) (442:442:442))
        (IOPATH datac combout (292:292:292) (292:292:292))
        (IOPATH datad combout (114:114:114) (114:114:114))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|U1\|u1\|rbr_3_.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datac (534:534:534) (559:559:559))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|U1\|u1\|rbr_3_.lereg)
    (DELAY
      (ABSOLUTE
        (PORT datac (649:649:649) (674:674:674))
        (PORT aclr (4823:4823:4823) (4890:4890:4890))
        (PORT clk (4293:4293:4293) (4319:4319:4319))
        (PORT ena (2710:2710:2710) (2808:2808:2808))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datac (posedge clk) (37:37:37))
      (SETUP ena (posedge clk) (37:37:37))
      (HOLD datac (posedge clk) (15:15:15))
      (HOLD ena (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|U1\|u1\