📄 uart_if_v.sdo

📁 this is a sample about UART transmission,it s default installation is D:RedLogicRCII_samples, and th
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// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.


// 
// Device: Altera EP1C12Q240C8 Package PQFP240
// 

// 
// This SDF file should be used for ModelSim (Verilog HDL output from Quartus II) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "uart_if_rom")
  (DATE "08/29/2007 17:06:01")
  (VENDOR "Altera")
  (PROGRAM "Quartus II")
  (VERSION "Version 5.0 Build 148 04/26/2005 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst5\|acc\[12\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst5\|acc\[12\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1741:1741:1741) (1721:1721:1721))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|cnt\[15\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (527:527:527) (538:538:538))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst2\|cnt\[15\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4290:4290:4290) (4319:4319:4319))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst5\|acc\[11\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (499:499:499) (510:510:510))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst5\|acc\[11\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1741:1741:1741) (1721:1721:1721))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|cnt\[14\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (515:515:515) (529:529:529))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst2\|cnt\[14\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4290:4290:4290) (4319:4319:4319))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst5\|acc\[10\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (483:483:483) (498:498:498))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout (583:583:583) (583:583:583))
        (IOPATH cin cout (136:136:136) (136:136:136))
        (IOPATH cin0 cout (178:178:178) (178:178:178))
        (IOPATH cin1 cout (157:157:157) (157:157:157))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst5\|acc\[10\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1741:1741:1741) (1721:1721:1721))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|cnt\[13\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (499:499:499) (510:510:510))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (839:839:839) (839:839:839))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst2\|cnt\[13\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4290:4290:4290) (4319:4319:4319))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst5\|acc\[9\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (500:500:500) (513:513:513))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout0 (423:423:423) (423:423:423))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH datab cout1 (432:432:432) (432:432:432))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst5\|acc\[9\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1741:1741:1741) (1721:1721:1721))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|cnt_3_.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (524:524:524) (535:535:535))
        (PORT datab (521:521:521) (528:528:528))
        (PORT datac (511:511:511) (542:542:542))
        (PORT datad (569:569:569) (558:558:558))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datac regin (478:478:478) (478:478:478))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|cnt_3_.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (4790:4790:4790) (4856:4856:4856))
        (PORT clk (4257:4257:4257) (4285:4285:4285))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst2\|cnt\[12\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (483:483:483) (498:498:498))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH datab cout (583:583:583) (583:583:583))
        (IOPATH cin cout (136:136:136) (136:136:136))
        (IOPATH cin0 cout (178:178:178) (178:178:178))
        (IOPATH cin1 cout (157:157:157) (157:157:157))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst2\|cnt\[12\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (4290:4290:4290) (4319:4319:4319))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst5\|acc\[8\]\~I.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT dataa (512:512:512) (529:529:529))
        (IOPATH dataa regin (738:738:738) (738:738:738))
        (IOPATH cin regin (898:898:898) (898:898:898))
        (IOPATH cin0 regin (783:783:783) (783:783:783))
        (IOPATH cin1 regin (787:787:787) (787:787:787))
        (IOPATH dataa cout0 (564:564:564) (564:564:564))
        (IOPATH cin0 cout0 (78:78:78) (78:78:78))
        (IOPATH dataa cout1 (575:575:575) (575:575:575))
        (IOPATH cin1 cout1 (80:80:80) (80:80:80))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst5\|acc\[8\]\~I.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (898:898:898) (898:898:898))
        (PORT clk (1741:1741:1741) (1721:1721:1721))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|cnt_0_.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datad (561:561:561) (553:553:553))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|cnt_0_.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (4790:4790:4790) (4856:4856:4856))
        (PORT clk (4257:4257:4257) (4285:4285:4285))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
    )
  )
  (CELL
    (CELLTYPE "cyclone_asynch_lcell")
    (INSTANCE inst\|cnt_1_.lecomb)
    (DELAY
      (ABSOLUTE
        (PORT datab (516:516:516) (522:522:522))
        (PORT datad (563:563:563) (553:553:553))
        (IOPATH datab regin (607:607:607) (607:607:607))
        (IOPATH datad regin (309:309:309) (309:309:309))
      )
    )
  )
  (CELL
    (CELLTYPE "cyclone_lcell_register")
    (INSTANCE inst\|cnt_1_.lereg)
    (DELAY
      (ABSOLUTE
        (PORT aclr (4790:4790:4790) (4856:4856:4856))
        (PORT clk (4257:4257:4257) (4285:4285:4285))
        (IOPATH (posedge clk) regout (224:224:224) (224:224:224))
        (IOPATH (posedge aclr) regout (283:283:283) (283:283:283))
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (37:37:37))
      (HOLD datain (posedge clk) (15:15:15))
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