uart_post.cr.mti

this is a sample about UART transmission,it s default installation is D:RedLogicRCII_samples, and th

J:/NewProj/3DConvertor/UART/physical/simulation/modelsim/uart_if.vo {1 {vlog -work work J:/NewProj/3DConvertor/UART/physical/simulation/modelsim/uart_if.vo
Model Technology ModelSim SE vlog 5.8b Compiler 2004.01 Jan 26 2004
-- Compiling module uart_if

Top level modules:
	uart_if

} {} {}} J:/NewProj/3DConvertor/UART/src/uart.v {1 {vlog -work work J:/NewProj/3DConvertor/UART/src/uart.v
Model Technology ModelSim SE vlog 5.8b Compiler 2004.01 Jan 26 2004
-- Compiling module uart

Top level modules:
	uart

} {} {}} J:/NewProj/3DConvertor/UART/src/uart_tb.v {1 {vlog -work work J:/NewProj/3DConvertor/UART/src/uart_tb.v
Model Technology ModelSim SE vlog 5.8b Compiler 2004.01 Jan 26 2004
-- Compiling module UART_tb

Top level modules:
	UART_tb

} {} {}} J:/NewProj/3DConvertor/UART/src/rcvr.v {1 {vlog -work work J:/NewProj/3DConvertor/UART/src/rcvr.v
Model Technology ModelSim SE vlog 5.8b Compiler 2004.01 Jan 26 2004
-- Compiling module rcvr

Top level modules:
	rcvr

} {} {}} J:/NewProj/3DConvertor/UART/src/txmit.v {1 {vlog -work work J:/NewProj/3DConvertor/UART/src/txmit.v
Model Technology ModelSim SE vlog 5.8b Compiler 2004.01 Jan 26 2004
-- Compiling module txmit

Top level modules:
	txmit

} {} {}} J:/NewProj/3DConvertor/UART/physical/simulation/modelsim/cyclone_atoms.v {1 {vlog -work work J:/NewProj/3DConvertor/UART/physical/simulation/modelsim/cyclone_atoms.v
Model Technology ModelSim SE vlog 5.8b Compiler 2004.01 Jan 26 2004
-- Compiling UDP PRIM_DFFE
-- Compiling module dffe
-- Compiling module latch
-- Compiling module mux21
-- Compiling module mux41
-- Compiling module and1
-- Compiling module and16
-- Compiling module bmux21
-- Compiling module b17mux21
-- Compiling module nmux21
-- Compiling module b5mux21
-- Compiling module cyclone_asynch_lcell
-- Compiling module cyclone_lcell_register
-- Compiling module cyclone_lcell
-- Compiling module cyclone_ram_register
-- Compiling module cyclone_ram_clear
-- Compiling module cyclone_ram_internal
-- Compiling module cyclone_ram_block
-- Compiling module m_cntr
-- Compiling module n_cntr
-- Compiling module scale_cntr
-- Compiling module pll_reg
-- Compiling module cyclone_pll
-- Compiling module cyclone_dll
-- Compiling module cyclone_jtag
-- Compiling module cyclone_crcblock
-- Compiling module cyclone_asynch_io
-- Compiling module cyclone_io
-- Compiling module cyclone_asmiblock

Top level modules:
	latch
	mux41
	and1
	and16
	bmux21
	b17mux21
	nmux21
	b5mux21
	cyclone_lcell
	cyclone_ram_block
	cyclone_pll
	cyclone_dll
	cyclone_jtag
	cyclone_crcblock
	cyclone_io
	cyclone_asmiblock

} {} {}}