_primary.vhd

来自「this is a sample about UART transmission」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity uart_if_rom is
    port(
        rst_n           : in     vl_logic;
        MCLK            : in     vl_logic;
        rxd             : in     vl_logic;
        txd             : out    vl_logic
    );
end uart_if_rom;