sram.fit.qmsg

this is a sample about SRAM read/write transmission,it s default installation is D:RedLogicRCII_samp

{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements" {  } {  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] -- routed using non-global resources" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]" } } } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[5\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[5\] -- routed using non-global resources" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[5\]" } } } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\] -- routed using non-global resources" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[4\]" } } } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] -- routed using non-global resources" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] -- routed using non-global resources" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]" } } } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\] -- routed using non-global resources" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0] } "NODE_NAME" } }  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_dffex:RESET\|Q\[0\]" } } } } { "sld_dffex.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0] } "NODE_NAME" } }  } 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|clear_signal " "Info: Node sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|clear_signal uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[1\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[1\] -- routed using non-global resources" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[1\]" } } } } { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|word_counter\[0\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|word_counter\[0\] -- routed using non-global resources" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|word_counter[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|word_counter\[0\]" } } } } { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 35 -1 0 } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|word_counter[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\] -- routed using non-global resources" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\]" } } } } { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[2\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[2\] -- routed using non-global resources" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[2\]" } } } } { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] " "Info: Port clear -- assigned as a global for destination node sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\] -- routed using non-global resources" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[3\]" } } } } { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[3] } "NODE_NAME" } }  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|clear_signal } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|clear_signal" } } } } { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 36 -1 0 } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|clear_signal } "NODE_NAME" } }  } 0}
{ "Warning" "WFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "4 " "Warning: The following 4 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "sram_cs GND " "Info: Pin sram_cs has GND driving its datain port" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 23 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_cs" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_cs } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_cs } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "sram_be\[0\] GND " "Info: Pin sram_be\[0\] has GND driving its datain port" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_be\[0\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_be[0] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_be[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "sram_be\[1\] GND " "Info: Pin sram_be\[1\] has GND driving its datain port" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_be\[1\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_be[1] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_be[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "task_start VCC " "Info: Pin task_start has VCC driving its datain port" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 25 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "task_start" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { task_start } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { task_start } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: The following groups of pins have the same output enable" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP" "sram_rd~reg0 " "Info: The following pins have the same output enable: sram_rd~reg0" { { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sram_db\[0\] LVTTL " "Info: Type bidirectional pin sram_db\[0\] uses the LVTTL I/O standard" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_db\[0\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[0] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_db[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sram_db\[1\] LVTTL " "Info: Type bidirectional pin sram_db\[1\] uses the LVTTL I/O standard" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_db\[1\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[1] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_db[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sram_db\[2\] LVTTL " "Info: Type bidirectional pin sram_db\[2\] uses the LVTTL I/O standard" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_db\[2\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[2] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_db[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sram_db\[3\] LVTTL " "Info: Type bidirectional pin sram_db\[3\] uses the LVTTL I/O standard" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_db\[3\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[3] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_db[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sram_db\[4\] LVTTL " "Info: Type bidirectional pin sram_db\[4\] uses the LVTTL I/O standard" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_db\[4\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[4] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_db[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sram_db\[5\] LVTTL " "Info: Type bidirectional pin sram_db\[5\] uses the LVTTL I/O standard" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_db\[5\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[5] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_db[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sram_db\[6\] LVTTL " "Info: Type bidirectional pin sram_db\[6\] uses the LVTTL I/O standard" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_db\[6\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[6] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_db[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sram_db\[7\] LVTTL " "Info: Type bidirectional pin sram_db\[7\] uses the LVTTL I/O standard" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_db\[7\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[7] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_db[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sram_db\[8\] LVTTL " "Info: Type bidirectional pin sram_db\[8\] uses the LVTTL I/O standard" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_db\[8\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[8] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_db[8] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sram_db\[9\] LVTTL " "Info: Type bidirectional pin sram_db\[9\] uses the LVTTL I/O standard" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_db\[9\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[9] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_db[9] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sram_db\[10\] LVTTL " "Info: Type bidirectional pin sram_db\[10\] uses the LVTTL I/O standard" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_db\[10\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[10] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_db[10] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sram_db\[11\] LVTTL " "Info: Type bidirectional pin sram_db\[11\] uses the LVTTL I/O standard" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_db\[11\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[11] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_db[11] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sram_db\[12\] LVTTL " "Info: Type bidirectional pin sram_db\[12\] uses the LVTTL I/O standard" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_db\[12\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[12] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_db[12] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sram_db\[13\] LVTTL " "Info: Type bidirectional pin sram_db\[13\] uses the LVTTL I/O standard" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_db\[13\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[13] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_db[13] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sram_db\[14\] LVTTL " "Info: Type bidirectional pin sram_db\[14\] uses the LVTTL I/O standard" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_db\[14\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[14] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_db[14] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sram_db\[15\] LVTTL " "Info: Type bidirectional pin sram_db\[15\] uses the LVTTL I/O standard" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "sram_db\[15\]" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[15] } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { sram_db[15] } "NODE_NAME" } }  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 27 23:17:29 2005 " "Info: Processing ended: Mon Jun 27 23:17:29 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:31 " "Info: Elapsed time: 00:00:31" {  } {  } 0}  } {  } 0}