sram.fit.qmsg

this is a sample about SRAM read/write transmission,it s default installation is D:RedLogicRCII_samp

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~TCKUTAP\" to use Global clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } } { "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/SRAM.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clk_2 Global clock " "Info: Automatically promoted some destinations of signal \"clk_2\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clk_2 " "Info: Destination \"clk_2\" may be non-global or may not use global clock" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 41 -1 0 } }  } 0}  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 41 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "rst Global clock in PIN 131 " "Info: Automatically promoted some destinations of signal \"rst\" to use Global clock in PIN 131" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[0\] " "Info: Destination \"sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[0\]\" may be non-global or may not use global clock" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0}  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 14 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_signaltap:auto_signaltap_0\|reset_all Global clock " "Info: Automatically promoted some destinations of signal \"sld_signaltap:auto_signaltap_0\|reset_all\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~29 " "Info: Destination \"sld_signaltap:auto_signaltap_0\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~29\" may be non-global or may not use global clock" {  } { { "sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 415 -1 0 } }  } 0}  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 415 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0 Global clock " "Info: Automatically promoted signal \"sld_hub:sld_hub_inst\|CLEAR_SIGNAL~0\" to use Global clock" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 307 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|clear_signal Global clock " "Info: Automatically promoted signal \"sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|clear_signal\" to use Global clock" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 36 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\]\" may be non-global or may not use global clock" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" may be non-global or may not use global clock" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } }  } 0}  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1014 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}