sram.map.qmsg

this is a sample about SRAM read/write transmission,it s default installation is D:RedLogicRCII_samp

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_compare " "Info: Found entity 1: lpm_compare" {  } { { "lpm_compare.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_compare.tdf" 262 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/comptree.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/comptree.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 comptree " "Info: Found entity 1: comptree" {  } { { "comptree.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/comptree.tdf" 102 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpchain " "Info: Found entity 1: cmpchain" {  } { { "cmpchain.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 84 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_acquisition_buffer-rtl " "Info: Found design unit 1: sld_acquisition_buffer-rtl" {  } { { "sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 73 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_offload_buffer_mgr-rtl " "Info: Found design unit 2: sld_offload_buffer_mgr-rtl" {  } { { "sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 308 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_acquisition_buffer " "Info: Found entity 1: sld_acquisition_buffer" {  } { { "sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 46 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_offload_buffer_mgr " "Info: Found entity 2: sld_offload_buffer_mgr" {  } { { "sld_acquisition_buffer.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_acquisition_buffer.vhd" 271 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_nt9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_nt9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_nt9 " "Info: Found entity 1: cntr_nt9" {  } { { "db/cntr_nt9.tdf" "" { Text "D:/RedLogic/RCII_samples/SRAM/Proj/db/cntr_nt9.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_ff " "Info: Found entity 1: lpm_ff" {  } { { "lpm_ff.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_ff.tdf" 46 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_rh92.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_rh92.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_rh92 " "Info: Found entity 1: altsyncram_rh92" {  } { { "db/altsyncram_rh92.tdf" "" { Text "D:/RedLogic/RCII_samples/SRAM/Proj/db/altsyncram_rh92.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_cv7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_cv7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_cv7 " "Info: Found entity 1: cntr_cv7" {  } { { "db/cntr_cv7.tdf" "" { Text "D:/RedLogic/RCII_samples/SRAM/Proj/db/cntr_cv7.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_dn7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_dn7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_dn7 " "Info: Found entity 1: cntr_dn7" {  } { { "db/cntr_dn7.tdf" "" { Text "D:/RedLogic/RCII_samples/SRAM/Proj/db/cntr_dn7.tdf" 25 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Info: Analysis and Synthesis generated SignalTap II or debug node instance \"auto_signaltap_0\"" { { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|clkin acq_clk " "Info: Source node \"\|sram_test\|clkin\" connects to port \"acq_clk\"" {  } { { "../Src/sram_test.v" "clkin" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 15 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|rst acq_trigger_in\[0\] " "Info: Source node \"\|sram_test\|rst\" connects to port \"acq_trigger_in\[0\]\"" {  } { { "../Src/sram_test.v" "rst" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 14 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|rst acq_data_in\[0\] " "Info: Source node \"\|sram_test\|rst\" connects to port \"acq_data_in\[0\]\"" {  } { { "../Src/sram_test.v" "rst" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 14 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[0\] acq_trigger_in\[1\] " "Info: Source node \"\|sram_test\|sram_ab\[0\]\" connects to port \"acq_trigger_in\[1\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[0\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[0\] acq_data_in\[1\] " "Info: Source node \"\|sram_test\|sram_ab\[0\]\" connects to port \"acq_data_in\[1\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[0\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[10\] acq_trigger_in\[2\] " "Info: Source node \"\|sram_test\|sram_ab\[10\]\" connects to port \"acq_trigger_in\[2\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[10\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[10\] acq_data_in\[2\] " "Info: Source node \"\|sram_test\|sram_ab\[10\]\" connects to port \"acq_data_in\[2\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[10\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[11\] acq_trigger_in\[3\] " "Info: Source node \"\|sram_test\|sram_ab\[11\]\" connects to port \"acq_trigger_in\[3\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[11\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[11\] acq_data_in\[3\] " "Info: Source node \"\|sram_test\|sram_ab\[11\]\" connects to port \"acq_data_in\[3\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[11\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[12\] acq_trigger_in\[4\] " "Info: Source node \"\|sram_test\|sram_ab\[12\]\" connects to port \"acq_trigger_in\[4\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[12\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[12\] acq_data_in\[4\] " "Info: Source node \"\|sram_test\|sram_ab\[12\]\" connects to port \"acq_data_in\[4\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[12\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[13\] acq_trigger_in\[5\] " "Info: Source node \"\|sram_test\|sram_ab\[13\]\" connects to port \"acq_trigger_in\[5\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[13\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[13\] acq_data_in\[5\] " "Info: Source node \"\|sram_test\|sram_ab\[13\]\" connects to port \"acq_data_in\[5\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[13\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[14\] acq_trigger_in\[6\] " "Info: Source node \"\|sram_test\|sram_ab\[14\]\" connects to port \"acq_trigger_in\[6\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[14\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[14\] acq_data_in\[6\] " "Info: Source node \"\|sram_test\|sram_ab\[14\]\" connects to port \"acq_data_in\[6\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[14\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[15\] acq_trigger_in\[7\] " "Info: Source node \"\|sram_test\|sram_ab\[15\]\" connects to port \"acq_trigger_in\[7\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[15\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[15\] acq_data_in\[7\] " "Info: Source node \"\|sram_test\|sram_ab\[15\]\" connects to port \"acq_data_in\[7\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[15\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[16\] acq_trigger_in\[8\] " "Info: Source node \"\|sram_test\|sram_ab\[16\]\" connects to port \"acq_trigger_in\[8\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[16\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[16\] acq_data_in\[8\] " "Info: Source node \"\|sram_test\|sram_ab\[16\]\" connects to port \"acq_data_in\[8\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[16\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[17\] acq_trigger_in\[9\] " "Info: Source node \"\|sram_test\|sram_ab\[17\]\" connects to port \"acq_trigger_in\[9\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[17\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[17\] acq_data_in\[9\] " "Info: Source node \"\|sram_test\|sram_ab\[17\]\" connects to port \"acq_data_in\[9\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[17\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[1\] acq_trigger_in\[10\] " "Info: Source node \"\|sram_test\|sram_ab\[1\]\" connects to port \"acq_trigger_in\[10\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[1\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[1\] acq_data_in\[10\] " "Info: Source node \"\|sram_test\|sram_ab\[1\]\" connects to port \"acq_data_in\[10\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[1\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[2\] acq_trigger_in\[11\] " "Info: Source node \"\|sram_test\|sram_ab\[2\]\" connects to port \"acq_trigger_in\[11\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[2\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[2\] acq_data_in\[11\] " "Info: Source node \"\|sram_test\|sram_ab\[2\]\" connects to port \"acq_data_in\[11\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[2\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[3\] acq_trigger_in\[12\] " "Info: Source node \"\|sram_test\|sram_ab\[3\]\" connects to port \"acq_trigger_in\[12\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[3\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[3\] acq_data_in\[12\] " "Info: Source node \"\|sram_test\|sram_ab\[3\]\" connects to port \"acq_data_in\[12\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[3\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[4\] acq_trigger_in\[13\] " "Info: Source node \"\|sram_test\|sram_ab\[4\]\" connects to port \"acq_trigger_in\[13\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[4\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[4\] acq_data_in\[13\] " "Info: Source node \"\|sram_test\|sram_ab\[4\]\" connects to port \"acq_data_in\[13\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[4\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[5\] acq_trigger_in\[14\] " "Info: Source node \"\|sram_test\|sram_ab\[5\]\" connects to port \"acq_trigger_in\[14\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[5\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[5\] acq_data_in\[14\] " "Info: Source node \"\|sram_test\|sram_ab\[5\]\" connects to port \"acq_data_in\[14\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[5\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[6\] acq_trigger_in\[15\] " "Info: Source node \"\|sram_test\|sram_ab\[6\]\" connects to port \"acq_trigger_in\[15\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[6\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[6\] acq_data_in\[15\] " "Info: Source node \"\|sram_test\|sram_ab\[6\]\" connects to port \"acq_data_in\[15\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[6\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[7\] acq_trigger_in\[16\] " "Info: Source node \"\|sram_test\|sram_ab\[7\]\" connects to port \"acq_trigger_in\[16\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[7\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[7\] acq_data_in\[16\] " "Info: Source node \"\|sram_test\|sram_ab\[7\]\" connects to port \"acq_data_in\[16\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[7\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[8\] acq_trigger_in\[17\] " "Info: Source node \"\|sram_test\|sram_ab\[8\]\" connects to port \"acq_trigger_in\[17\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[8\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[8\] acq_data_in\[17\] " "Info: Source node \"\|sram_test\|sram_ab\[8\]\" connects to port \"acq_data_in\[17\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[8\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[9\] acq_trigger_in\[18\] " "Info: Source node \"\|sram_test\|sram_ab\[9\]\" connects to port \"acq_trigger_in\[18\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[9\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_ab\[9\] acq_data_in\[18\] " "Info: Source node \"\|sram_test\|sram_ab\[9\]\" connects to port \"acq_data_in\[18\]\"" {  } { { "../Src/sram_test.v" "sram_ab\[9\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 17 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_cs acq_trigger_in\[19\] " "Info: Source node \"\|sram_test\|sram_cs\" connects to port \"acq_trigger_in\[19\]\"" {  } { { "../Src/sram_test.v" "sram_cs" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 23 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_cs acq_data_in\[19\] " "Info: Source node \"\|sram_test\|sram_cs\" connects to port \"acq_data_in\[19\]\"" {  } { { "../Src/sram_test.v" "sram_cs" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 23 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[0\] acq_trigger_in\[20\] " "Info: Source node \"\|sram_test\|sram_db\[0\]\" connects to port \"acq_trigger_in\[20\]\"" {  } { { "../Src/sram_test.v" "sram_db\[0\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[0\] acq_data_in\[20\] " "Info: Source node \"\|sram_test\|sram_db\[0\]\" connects to port \"acq_data_in\[20\]\"" {  } { { "../Src/sram_test.v" "sram_db\[0\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[10\] acq_trigger_in\[21\] " "Info: Source node \"\|sram_test\|sram_db\[10\]\" connects to port \"acq_trigger_in\[21\]\"" {  } { { "../Src/sram_test.v" "sram_db\[10\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[10\] acq_data_in\[21\] " "Info: Source node \"\|sram_test\|sram_db\[10\]\" connects to port \"acq_data_in\[21\]\"" {  } { { "../Src/sram_test.v" "sram_db\[10\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[11\] acq_trigger_in\[22\] " "Info: Source node \"\|sram_test\|sram_db\[11\]\" connects to port \"acq_trigger_in\[22\]\"" {  } { { "../Src/sram_test.v" "sram_db\[11\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[11\] acq_data_in\[22\] " "Info: Source node \"\|sram_test\|sram_db\[11\]\" connects to port \"acq_data_in\[22\]\"" {  } { { "../Src/sram_test.v" "sram_db\[11\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[12\] acq_trigger_in\[23\] " "Info: Source node \"\|sram_test\|sram_db\[12\]\" connects to port \"acq_trigger_in\[23\]\"" {  } { { "../Src/sram_test.v" "sram_db\[12\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[12\] acq_data_in\[23\] " "Info: Source node \"\|sram_test\|sram_db\[12\]\" connects to port \"acq_data_in\[23\]\"" {  } { { "../Src/sram_test.v" "sram_db\[12\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[13\] acq_trigger_in\[24\] " "Info: Source node \"\|sram_test\|sram_db\[13\]\" connects to port \"acq_trigger_in\[24\]\"" {  } { { "../Src/sram_test.v" "sram_db\[13\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[13\] acq_data_in\[24\] " "Info: Source node \"\|sram_test\|sram_db\[13\]\" connects to port \"acq_data_in\[24\]\"" {  } { { "../Src/sram_test.v" "sram_db\[13\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[14\] acq_trigger_in\[25\] " "Info: Source node \"\|sram_test\|sram_db\[14\]\" connects to port \"acq_trigger_in\[25\]\"" {  } { { "../Src/sram_test.v" "sram_db\[14\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[14\] acq_data_in\[25\] " "Info: Source node \"\|sram_test\|sram_db\[14\]\" connects to port \"acq_data_in\[25\]\"" {  } { { "../Src/sram_test.v" "sram_db\[14\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[15\] acq_trigger_in\[26\] " "Info: Source node \"\|sram_test\|sram_db\[15\]\" connects to port \"acq_trigger_in\[26\]\"" {  } { { "../Src/sram_test.v" "sram_db\[15\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[15\] acq_data_in\[26\] " "Info: Source node \"\|sram_test\|sram_db\[15\]\" connects to port \"acq_data_in\[26\]\"" {  } { { "../Src/sram_test.v" "sram_db\[15\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[1\] acq_trigger_in\[27\] " "Info: Source node \"\|sram_test\|sram_db\[1\]\" connects to port \"acq_trigger_in\[27\]\"" {  } { { "../Src/sram_test.v" "sram_db\[1\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[1\] acq_data_in\[27\] " "Info: Source node \"\|sram_test\|sram_db\[1\]\" connects to port \"acq_data_in\[27\]\"" {  } { { "../Src/sram_test.v" "sram_db\[1\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[2\] acq_trigger_in\[28\] " "Info: Source node \"\|sram_test\|sram_db\[2\]\" connects to port \"acq_trigger_in\[28\]\"" {  } { { "../Src/sram_test.v" "sram_db\[2\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[2\] acq_data_in\[28\] " "Info: Source node \"\|sram_test\|sram_db\[2\]\" connects to port \"acq_data_in\[28\]\"" {  } { { "../Src/sram_test.v" "sram_db\[2\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[3\] acq_trigger_in\[29\] " "Info: Source node \"\|sram_test\|sram_db\[3\]\" connects to port \"acq_trigger_in\[29\]\"" {  } { { "../Src/sram_test.v" "sram_db\[3\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[3\] acq_data_in\[29\] " "Info: Source node \"\|sram_test\|sram_db\[3\]\" connects to port \"acq_data_in\[29\]\"" {  } { { "../Src/sram_test.v" "sram_db\[3\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[4\] acq_trigger_in\[30\] " "Info: Source node \"\|sram_test\|sram_db\[4\]\" connects to port \"acq_trigger_in\[30\]\"" {  } { { "../Src/sram_test.v" "sram_db\[4\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[4\] acq_data_in\[30\] " "Info: Source node \"\|sram_test\|sram_db\[4\]\" connects to port \"acq_data_in\[30\]\"" {  } { { "../Src/sram_test.v" "sram_db\[4\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[5\] acq_trigger_in\[31\] " "Info: Source node \"\|sram_test\|sram_db\[5\]\" connects to port \"acq_trigger_in\[31\]\"" {  } { { "../Src/sram_test.v" "sram_db\[5\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[5\] acq_data_in\[31\] " "Info: Source node \"\|sram_test\|sram_db\[5\]\" connects to port \"acq_data_in\[31\]\"" {  } { { "../Src/sram_test.v" "sram_db\[5\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[6\] acq_trigger_in\[32\] " "Info: Source node \"\|sram_test\|sram_db\[6\]\" connects to port \"acq_trigger_in\[32\]\"" {  } { { "../Src/sram_test.v" "sram_db\[6\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[6\] acq_data_in\[32\] " "Info: Source node \"\|sram_test\|sram_db\[6\]\" connects to port \"acq_data_in\[32\]\"" {  } { { "../Src/sram_test.v" "sram_db\[6\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[7\] acq_trigger_in\[33\] " "Info: Source node \"\|sram_test\|sram_db\[7\]\" connects to port \"acq_trigger_in\[33\]\"" {  } { { "../Src/sram_test.v" "sram_db\[7\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[7\] acq_data_in\[33\] " "Info: Source node \"\|sram_test\|sram_db\[7\]\" connects to port \"acq_data_in\[33\]\"" {  } { { "../Src/sram_test.v" "sram_db\[7\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[8\] acq_trigger_in\[34\] " "Info: Source node \"\|sram_test\|sram_db\[8\]\" connects to port \"acq_trigger_in\[34\]\"" {  } { { "../Src/sram_test.v" "sram_db\[8\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[8\] acq_data_in\[34\] " "Info: Source node \"\|sram_test\|sram_db\[8\]\" connects to port \"acq_data_in\[34\]\"" {  } { { "../Src/sram_test.v" "sram_db\[8\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[9\] acq_trigger_in\[35\] " "Info: Source node \"\|sram_test\|sram_db\[9\]\" connects to port \"acq_trigger_in\[35\]\"" {  } { { "../Src/sram_test.v" "sram_db\[9\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_db\[9\] acq_data_in\[35\] " "Info: Source node \"\|sram_test\|sram_db\[9\]\" connects to port \"acq_data_in\[35\]\"" {  } { { "../Src/sram_test.v" "sram_db\[9\]" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_rd acq_trigger_in\[36\] " "Info: Source node \"\|sram_test\|sram_rd\" connects to port \"acq_trigger_in\[36\]\"" {  } { { "../Src/sram_test.v" "sram_rd" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 22 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_rd acq_data_in\[36\] " "Info: Source node \"\|sram_test\|sram_rd\" connects to port \"acq_data_in\[36\]\"" {  } { { "../Src/sram_test.v" "sram_rd" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 22 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_rd trigger_in " "Info: Source node \"\|sram_test\|sram_rd\" connects to port \"trigger_in\"" {  } { { "../Src/sram_test.v" "sram_rd" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 22 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_wr acq_trigger_in\[37\] " "Info: Source node \"\|sram_test\|sram_wr\" connects to port \"acq_trigger_in\[37\]\"" {  } { { "../Src/sram_test.v" "sram_wr" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 21 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|sram_wr acq_data_in\[37\] " "Info: Source node \"\|sram_test\|sram_wr\" connects to port \"acq_data_in\[37\]\"" {  } { { "../Src/sram_test.v" "sram_wr" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 21 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|task_finish acq_trigger_in\[38\] " "Info: Source node \"\|sram_test\|task_finish\" connects to port \"acq_trigger_in\[38\]\"" {  } { { "../Src/sram_test.v" "task_finish" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 26 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|task_finish acq_data_in\[38\] " "Info: Source node \"\|sram_test\|task_finish\" connects to port \"acq_data_in\[38\]\"" {  } { { "../Src/sram_test.v" "task_finish" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 26 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|task_start acq_trigger_in\[39\] " "Info: Source node \"\|sram_test\|task_start\" connects to port \"acq_trigger_in\[39\]\"" {  } { { "../Src/sram_test.v" "task_start" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 25 -1 0 } }  } 0} { "Info" "ISGN_AE_CONNECT_TO_PORT" "\|sram_test\|task_start acq_data_in\[39\] " "Info: Source node \"\|sram_test\|task_start\" connects to port \"acq_data_in\[39\]\"" {  } { { "../Src/sram_test.v" "task_start" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 25 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 166 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 1012 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 997 -1 0 } }  } 0}  } {  } 0}