sram.map.qmsg

this is a sample about SRAM read/write transmission,it s default installation is D:RedLogicRCII_samp

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 27 23:16:23 2005 " "Info: Processing started: Mon Jun 27 23:16:23 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SRAM -c SRAM " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SRAM -c SRAM" {  } {  } 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "sram_test.v(58) " "Warning: (10273) Verilog HDL warning at sram_test.v(58): extended using \"x\" or \"z\"" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 58 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 sram_test.v(102) " "Warning: (10229) Verilog HDL Expression warning at sram_test.v(102): truncated literal to match 16 bits" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 102 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "16 sram_test.v(139) " "Warning: (10229) Verilog HDL Expression warning at sram_test.v(139): truncated literal to match 16 bits" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 139 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../Src/sram_test.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../Src/sram_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 sram_test " "Info: Found entity 1: sram_test" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sram_test " "Info: Elaborating entity \"sram_test\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 sram_test.v(56) " "Warning: Verilog HDL assignment warning at sram_test.v(56): truncated value with size 32 to match size of target (1)" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 56 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 sram_test.v(58) " "Warning: Verilog HDL assignment warning at sram_test.v(58): truncated value with size 32 to match size of target (16)" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 58 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 sram_test.v(109) " "Warning: Verilog HDL assignment warning at sram_test.v(109): truncated value with size 32 to match size of target (1)" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 109 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 sram_test.v(110) " "Warning: Verilog HDL assignment warning at sram_test.v(110): truncated value with size 32 to match size of target (1)" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 110 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 18 sram_test.v(113) " "Warning: Verilog HDL assignment warning at sram_test.v(113): truncated value with size 32 to match size of target (18)" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 113 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 sram_test.v(114) " "Warning: Verilog HDL assignment warning at sram_test.v(114): truncated value with size 32 to match size of target (16)" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 114 0 0 } }  } 0}