sram.tan.qmsg

this is a sample about SRAM read/write transmission,it s default installation is D:RedLogicRCII_samp

{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.124 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 2.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y13_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.124 ns) 2.124 ns altera_reserved_tdo 2 PIN PIN_149 0 " "Info: 2: + IC(0.000 ns) + CELL(2.124 ns) = 2.124 ns; Loc. = PIN_149; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 100.00 % " "Info: Total cell delay = 2.124 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.124 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "sld_signaltap:auto_signaltap_0\|bypass_reg_out altera_internal_jtag altera_internal_jtag~TCKUTAP 1.939 ns register " "Info: th for register \"sld_signaltap:auto_signaltap_0\|bypass_reg_out\" (data pin = \"altera_internal_jtag\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 1.939 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.285 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.285 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 396 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 396; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.574 ns) + CELL(0.711 ns) 5.285 ns sld_signaltap:auto_signaltap_0\|bypass_reg_out 2 REG LC_X28_Y9_N8 1 " "Info: 2: + IC(4.574 ns) + CELL(0.711 ns) = 5.285 ns; Loc. = LC_X28_Y9_N8; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|bypass_reg_out'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "5.285 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|bypass_reg_out } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 420 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.45 % " "Info: Total cell delay = 0.711 ns ( 13.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.574 ns 86.55 % " "Info: Total interconnect delay = 4.574 ns ( 86.55 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "5.285 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|bypass_reg_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.285 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|bypass_reg_out } { 0.000ns 4.574ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 420 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.361 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.361 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag 1 PIN JTAG_X1_Y13_N1 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 9; PIN Node = 'altera_internal_jtag'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { altera_internal_jtag } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.246 ns) + CELL(0.115 ns) 3.361 ns sld_signaltap:auto_signaltap_0\|bypass_reg_out 2 REG LC_X28_Y9_N8 1 " "Info: 2: + IC(3.246 ns) + CELL(0.115 ns) = 3.361 ns; Loc. = LC_X28_Y9_N8; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|bypass_reg_out'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "3.361 ns" { altera_internal_jtag sld_signaltap:auto_signaltap_0|bypass_reg_out } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 420 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 3.42 % " "Info: Total cell delay = 0.115 ns ( 3.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.246 ns 96.58 % " "Info: Total interconnect delay = 3.246 ns ( 96.58 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "3.361 ns" { altera_internal_jtag sld_signaltap:auto_signaltap_0|bypass_reg_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.361 ns" { altera_internal_jtag sld_signaltap:auto_signaltap_0|bypass_reg_out } { 0.000ns 3.246ns } { 0.000ns 0.115ns } } }  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "5.285 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|bypass_reg_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.285 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|bypass_reg_out } { 0.000ns 4.574ns } { 0.000ns 0.711ns } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "3.361 ns" { altera_internal_jtag sld_signaltap:auto_signaltap_0|bypass_reg_out } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.361 ns" { altera_internal_jtag sld_signaltap:auto_signaltap_0|bypass_reg_out } { 0.000ns 3.246ns } { 0.000ns 0.115ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 27 23:17:41 2005 " "Info: Processing ended: Mon Jun 27 23:17:41 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}