sram.tan.qmsg

this is a sample about SRAM read/write transmission,it s default installation is D:RedLogicRCII_samp

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\] register sld_hub:sld_hub_inst\|hub_tdo 131.79 MHz 7.588 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 131.79 MHz between source register \"sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 7.588 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.535 ns + Longest register register " "Info: + Longest register to register delay is 3.535 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\] 1 REG LC_X28_Y11_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X28_Y11_N6; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\]'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.274 ns) + CELL(0.114 ns) 1.388 ns sld_hub:sld_hub_inst\|hub_tdo~248 2 COMB LC_X29_Y9_N9 1 " "Info: 2: + IC(1.274 ns) + CELL(0.114 ns) = 1.388 ns; Loc. = LC_X29_Y9_N9; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~248'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "1.388 ns" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~248 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.691 ns) + CELL(0.442 ns) 2.521 ns sld_hub:sld_hub_inst\|hub_tdo~249 3 COMB LC_X28_Y9_N5 1 " "Info: 3: + IC(0.691 ns) + CELL(0.442 ns) = 2.521 ns; Loc. = LC_X28_Y9_N5; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~249'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "1.133 ns" { sld_hub:sld_hub_inst|hub_tdo~248 sld_hub:sld_hub_inst|hub_tdo~249 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.407 ns) + CELL(0.607 ns) 3.535 ns sld_hub:sld_hub_inst\|hub_tdo 4 REG LC_X28_Y9_N3 0 " "Info: 4: + IC(0.407 ns) + CELL(0.607 ns) = 3.535 ns; Loc. = LC_X28_Y9_N3; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "1.014 ns" { sld_hub:sld_hub_inst|hub_tdo~249 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.163 ns 32.90 % " "Info: Total cell delay = 1.163 ns ( 32.90 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.372 ns 67.10 % " "Info: Total interconnect delay = 2.372 ns ( 67.10 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "3.535 ns" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~248 sld_hub:sld_hub_inst|hub_tdo~249 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.535 ns" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~248 sld_hub:sld_hub_inst|hub_tdo~249 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.274ns 0.691ns 0.407ns } { 0.000ns 0.114ns 0.442ns 0.607ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.002 ns - Smallest " "Info: - Smallest clock skew is 0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.285 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.285 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 396 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 396; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.574 ns) + CELL(0.711 ns) 5.285 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X28_Y9_N3 0 " "Info: 2: + IC(4.574 ns) + CELL(0.711 ns) = 5.285 ns; Loc. = LC_X28_Y9_N3; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "5.285 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.45 % " "Info: Total cell delay = 0.711 ns ( 13.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.574 ns 86.55 % " "Info: Total interconnect delay = 4.574 ns ( 86.55 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "5.285 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.285 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.574ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.283 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.283 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y13_N1 396 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y13_N1; Fanout = 396; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.572 ns) + CELL(0.711 ns) 5.283 ns sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\] 2 REG LC_X28_Y11_N6 1 " "Info: 2: + IC(4.572 ns) + CELL(0.711 ns) = 5.283 ns; Loc. = LC_X28_Y11_N6; Fanout = 1; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_rom_sr:crc_rom_sr\|WORD_SR\[0\]'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } "" } } { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 13.46 % " "Info: Total cell delay = 0.711 ns ( 13.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.572 ns 86.54 % " "Info: Total interconnect delay = 4.572 ns ( 86.54 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] } { 0.000ns 4.572ns } { 0.000ns 0.711ns } } }  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "5.285 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.285 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.574ns } { 0.000ns 0.711ns } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] } { 0.000ns 4.572ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_rom_sr.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_rom_sr.vhd" 33 -1 0 } } { "sld_hub.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "3.535 ns" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~248 sld_hub:sld_hub_inst|hub_tdo~249 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.535 ns" { sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo~248 sld_hub:sld_hub_inst|hub_tdo~249 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.274ns 0.691ns 0.407ns } { 0.000ns 0.114ns 0.442ns 0.607ns } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "5.285 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.285 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.574ns } { 0.000ns 0.711ns } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "5.283 ns" { altera_internal_jtag~TCKUTAP sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0] } { 0.000ns 4.572ns } { 0.000ns 0.711ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[22\] sram_db\[11\] clkin 7.452 ns register " "Info: tsu for register \"sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[22\]\" (data pin = \"sram_db\[11\]\", clock pin = \"clkin\") is 7.452 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.526 ns + Longest pin register " "Info: + Longest pin to register delay is 10.526 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sram_db\[11\] 1 PIN PIN_83 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_83; Fanout = 1; PIN Node = 'sram_db\[11\]'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sram_db[11] } "NODE_NAME" } "" } } { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns sram_db\[11\]~4 2 COMB IOC_X14_Y0_N1 2 " "Info: 2: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = IOC_X14_Y0_N1; Fanout = 2; COMB Node = 'sram_db\[11\]~4'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "1.475 ns" { sram_db[11] sram_db[11]~4 } "NODE_NAME" } "" } } { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(8.936 ns) + CELL(0.115 ns) 10.526 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[22\] 3 REG LC_X36_Y6_N1 3 " "Info: 3: + IC(8.936 ns) + CELL(0.115 ns) = 10.526 ns; Loc. = LC_X36_Y6_N1; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[22\]'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "9.051 ns" { sram_db[11]~4 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[22] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.590 ns 15.11 % " "Info: Total cell delay = 1.590 ns ( 15.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.936 ns 84.89 % " "Info: Total interconnect delay = 8.936 ns ( 84.89 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "10.526 ns" { sram_db[11] sram_db[11]~4 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[22] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.526 ns" { sram_db[11] sram_db[11]~4 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[22] } { 0.000ns 0.000ns 8.936ns } { 0.000ns 1.475ns 0.115ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 3.111 ns - Shortest register " "Info: - Shortest clock path from clock \"clkin\" to destination register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_153 386 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 386; CLK Node = 'clkin'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { clkin } "NODE_NAME" } "" } } { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[22\] 2 REG LC_X36_Y6_N1 3 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X36_Y6_N1; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|acq_trigger_in_reg\[22\]'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "1.642 ns" { clkin sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[22] } "NODE_NAME" } "" } } { "sld_signaltap.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_signaltap.vhd" 437 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 70.07 % " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns 29.93 % " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "3.111 ns" { clkin sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[22] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[22] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "10.526 ns" { sram_db[11] sram_db[11]~4 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[22] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "10.526 ns" { sram_db[11] sram_db[11]~4 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[22] } { 0.000ns 0.000ns 8.936ns } { 0.000ns 1.475ns 0.115ns } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "3.111 ns" { clkin sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[22] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[22] } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkin task_finish task_finish~reg0 17.485 ns register " "Info: tco from clock \"clkin\" to destination pin \"task_finish\" through register \"task_finish~reg0\" is 17.485 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 7.662 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to source register is 7.662 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_153 386 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 386; CLK Node = 'clkin'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { clkin } "NODE_NAME" } "" } } { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns clk_2 2 REG LC_X8_Y13_N5 59 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X8_Y13_N5; Fanout = 59; REG Node = 'clk_2'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "1.965 ns" { clkin clk_2 } "NODE_NAME" } "" } } { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 41 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.517 ns) + CELL(0.711 ns) 7.662 ns task_finish~reg0 3 REG LC_X39_Y3_N2 2 " "Info: 3: + IC(3.517 ns) + CELL(0.711 ns) = 7.662 ns; Loc. = LC_X39_Y3_N2; Fanout = 2; REG Node = 'task_finish~reg0'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "4.228 ns" { clk_2 task_finish~reg0 } "NODE_NAME" } "" } } { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 134 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 40.66 % " "Info: Total cell delay = 3.115 ns ( 40.66 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.547 ns 59.34 % " "Info: Total interconnect delay = 4.547 ns ( 59.34 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "7.662 ns" { clkin clk_2 task_finish~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.662 ns" { clkin clkin~out0 clk_2 task_finish~reg0 } { 0.000ns 0.000ns 1.030ns 3.517ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 134 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.599 ns + Longest register pin " "Info: + Longest register to pin delay is 9.599 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns task_finish~reg0 1 REG LC_X39_Y3_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X39_Y3_N2; Fanout = 2; REG Node = 'task_finish~reg0'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { task_finish~reg0 } "NODE_NAME" } "" } } { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(7.475 ns) + CELL(2.124 ns) 9.599 ns task_finish 2 PIN PIN_8 0 " "Info: 2: + IC(7.475 ns) + CELL(2.124 ns) = 9.599 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'task_finish'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "9.599 ns" { task_finish~reg0 task_finish } "NODE_NAME" } "" } } { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 26 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns 22.13 % " "Info: Total cell delay = 2.124 ns ( 22.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.475 ns 77.87 % " "Info: Total interconnect delay = 7.475 ns ( 77.87 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "9.599 ns" { task_finish~reg0 task_finish } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.599 ns" { task_finish~reg0 task_finish } { 0.000ns 7.475ns } { 0.000ns 2.124ns } } }  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "7.662 ns" { clkin clk_2 task_finish~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.662 ns" { clkin clkin~out0 clk_2 task_finish~reg0 } { 0.000ns 0.000ns 1.030ns 3.517ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "9.599 ns" { task_finish~reg0 task_finish } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "9.599 ns" { task_finish~reg0 task_finish } { 0.000ns 7.475ns } { 0.000ns 2.124ns } } }  } 0}