sram.tan.qmsg

this is a sample about SRAM read/write transmission,it s default installation is D:RedLogicRCII_samp

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clkin " "Info: Assuming node \"clkin\" is an undefined clock" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 15 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_2 " "Info: Detected ripple clock \"clk_2\" as buffer" {  } { { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 41 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_2" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkin register sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[3\] register sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 129.28 MHz 7.735 ns Internal " "Info: Clock \"clkin\" has Internal fmax of 129.28 MHz between source register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[3\]\" and destination register \"sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena\" (period= 7.735 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.473 ns + Longest register register " "Info: + Longest register to register delay is 7.473 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[3\] 1 REG LC_X38_Y11_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X38_Y11_N3; Fanout = 4; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[3\]'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_e29.tdf" "" { Text "D:/RedLogic/RCII_samples/SRAM/Proj/db/cntr_e29.tdf" 120 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.264 ns) + CELL(0.442 ns) 1.706 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~61 2 COMB LC_X38_Y10_N6 1 " "Info: 2: + IC(1.264 ns) + CELL(0.442 ns) = 1.706 ns; Loc. = LC_X38_Y10_N6; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~61'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "1.706 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~61 } "NODE_NAME" } "" } } { "cmpchain.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 116 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.433 ns) + CELL(0.590 ns) 2.729 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~62 3 COMB LC_X38_Y10_N7 1 " "Info: 3: + IC(0.433 ns) + CELL(0.590 ns) = 2.729 ns; Loc. = LC_X38_Y10_N7; Fanout = 1; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~62'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "1.023 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~61 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 } "NODE_NAME" } "" } } { "cmpchain.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 116 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.966 ns) + CELL(0.292 ns) 4.987 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~0 4 COMB LC_X38_Y10_N4 11 " "Info: 4: + IC(1.966 ns) + CELL(0.292 ns) = 4.987 ns; Loc. = LC_X38_Y10_N4; Fanout = 11; COMB Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_compare:\\non_zero_sample_depth_gen:segment_addr_compare\|comptree:comparator\|cmpchain:cmp_end\|comptree:comp\|comptree:sub_comptree\|comptree:sub_comptree\|cmpchain:cmp_end\|aeb_out~0'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "2.258 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 } "NODE_NAME" } "" } } { "cmpchain.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/cmpchain.tdf" 116 6 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.008 ns) + CELL(0.478 ns) 7.473 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 5 REG LC_X36_Y8_N6 12 " "Info: 5: + IC(2.008 ns) + CELL(0.478 ns) = 7.473 ns; Loc. = LC_X36_Y8_N6; Fanout = 12; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "2.486 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.802 ns 24.11 % " "Info: Total cell delay = 1.802 ns ( 24.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.671 ns 75.89 % " "Info: Total interconnect delay = 5.671 ns ( 75.89 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "7.473 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~61 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.473 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~61 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 1.264ns 0.433ns 1.966ns 2.008ns } { 0.000ns 0.442ns 0.590ns 0.292ns 0.478ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.001 ns - Smallest " "Info: - Smallest clock skew is -0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 3.111 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 3.111 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_153 386 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 386; CLK Node = 'clkin'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { clkin } "NODE_NAME" } "" } } { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.931 ns) + CELL(0.711 ns) 3.111 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena 2 REG LC_X36_Y8_N6 12 " "Info: 2: + IC(0.931 ns) + CELL(0.711 ns) = 3.111 ns; Loc. = LC_X36_Y8_N6; Fanout = 12; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|segment_write_addr_adv_ena'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "1.642 ns" { clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 70.07 % " "Info: Total cell delay = 2.180 ns ( 70.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.931 ns 29.93 % " "Info: Total interconnect delay = 0.931 ns ( 29.93 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "3.111 ns" { clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 3.112 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 3.112 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_153 386 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 386; CLK Node = 'clkin'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "" { clkin } "NODE_NAME" } "" } } { "../Src/sram_test.v" "" { Text "D:/RedLogic/RCII_samples/SRAM/Src/sram_test.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.932 ns) + CELL(0.711 ns) 3.112 ns sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[3\] 2 REG LC_X38_Y11_N3 4 " "Info: 2: + IC(0.932 ns) + CELL(0.711 ns) = 3.112 ns; Loc. = LC_X38_Y11_N3; Fanout = 4; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_ela_control:ela_control\|sld_ela_segment_mgr:\\gen_non_zero_sample_depth_segment:seg_mgr\|lpm_counter:\\non_zero_sample_depth_gen:segment_addr_counter\|cntr_e29:auto_generated\|safe_q\[3\]'" {  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "1.643 ns" { clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "db/cntr_e29.tdf" "" { Text "D:/RedLogic/RCII_samples/SRAM/Proj/db/cntr_e29.tdf" 120 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 70.05 % " "Info: Total cell delay = 2.180 ns ( 70.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.932 ns 29.95 % " "Info: Total interconnect delay = 0.932 ns ( 29.95 % )" {  } {  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "3.112 ns" { clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.112 ns" { clkin clkin~out0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] } { 0.000ns 0.000ns 0.932ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "3.111 ns" { clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "3.112 ns" { clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.112 ns" { clkin clkin~out0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] } { 0.000ns 0.000ns 0.932ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_e29.tdf" "" { Text "D:/RedLogic/RCII_samples/SRAM/Proj/db/cntr_e29.tdf" 120 8 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "sld_ela_control.vhd" "" { Text "c:/altera/quartus50/libraries/megafunctions/sld_ela_control.vhd" 1399 -1 0 } }  } 0}  } { { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "7.473 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~61 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.473 ns" { sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~61 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~62 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_compare:\non_zero_sample_depth_gen:segment_addr_compare|comptree:comparator|cmpchain:cmp_end|comptree:comp|comptree:sub_comptree|comptree:sub_comptree|cmpchain:cmp_end|aeb_out~0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 1.264ns 0.433ns 1.966ns 2.008ns } { 0.000ns 0.442ns 0.590ns 0.292ns 0.478ns } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "3.111 ns" { clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.111 ns" { clkin clkin~out0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena } { 0.000ns 0.000ns 0.931ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" "" { Report "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM_cmp.qrpt" Compiler "SRAM" "UNKNOWN" "V1" "D:/RedLogic/RCII_samples/SRAM/Proj/db/SRAM.quartus_db" { Floorplan "D:/RedLogic/RCII_samples/SRAM/Proj/" "" "3.112 ns" { clkin sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.112 ns" { clkin clkin~out0 sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] } { 0.000ns 0.000ns 0.932ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}