sram.tan.rpt

this is a sample about SRAM read/write transmission,it s default installation is D:RedLogicRCII_samp

programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                                                                                                    ; To                                                                                                                                                   ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 7.452 ns                         ; sram_db[11]                                                                                                                                                                                                             ; sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[22]                                                                                                ;                              ; clkin                        ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 17.485 ns                        ; task_finish~reg0                                                                                                                                                                                                        ; task_finish                                                                                                                                          ; clkin                        ;                              ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                                                                                                                ; altera_reserved_tdo                                                                                                                                  ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 1.939 ns                         ; altera_internal_jtag                                                                                                                                                                                                    ; sld_signaltap:auto_signaltap_0|bypass_reg_out                                                                                                        ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'clkin'                        ; N/A   ; None          ; 129.28 MHz ( period = 7.735 ns ) ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|lpm_counter:\non_zero_sample_depth_gen:segment_addr_counter|cntr_e29:auto_generated|safe_q[3] ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena ; clkin                        ; clkin                        ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 131.79 MHz ( period = 7.588 ns ) ; sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0]                                                                                                                                                         ; sld_hub:sld_hub_inst|hub_tdo                                                                                                                         ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                                                                                                                         ;                                                                                                                                                      ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;