fab_custom.c

树大根深三棱尽所标杆ssfsfsa fdsafs

	{"PADIR",	0xF400, 1, 0x00, /* Port A Direction Reg */
		{0, 0}, {0, 0}, {0, 0},
		""},
	{"PADATA",	0xF401, 1, 0x00, /* Port A Data Reg */
		{0, 0}, {0, 0}, {0, 0},
		""},
	{"PASEL",	0xF403, 1, 0x00, /* Port A Select Reg */
		{0, 0}, {0, 0}, {0, 0},
		""},

	{"PBDIR",	0xF408, 1, 0x00, /* Port B Direction Reg */
		{0, 0}, {0, 0}, {0, 0},
		""},
	{"PBDATA",	0xF409, 1, 0x00, /* Port B Data Reg */
		{0, 0}, {0, 0}, {0, 0},
		""},
	{"PBSEL",	0xF40B, 1, 0x00, /* Port B Select Reg */
		{0, 0}, {0, 0}, {0, 0},
		""},
#endif
	{"PCDIR",	0xF410, 1, 0x00, /* Port C Direction Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"MOCLK:1;UDS:1;LDS:1;:1;NMI:1;DTACK:1;WE:1;:1;"},
	{"PCDATA",	0xF411, 1, 0x00, /* Port C Data Reg */
		{pcdata_get, reg_put}, {0, 0}, {0, 0},
		"MOCLK:1;UDS:1;LDS:1;:1;NMI:1;DTACK:1;WE:1;:1;"},
	{"PCSEL",	0xF413, 1, 0x00, /* Port C Select Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"MOCLK:1;UDS:1;LDS:1;:1;NMI:1;DTACK:1;WE:1;:1;"},

	{"PDDIR",	0xF418, 1, 0x00, /* Port D Direction Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"BB0:1;B1:1;B2:1;B3:1;B4:1;B5:1;B6:1;B7:1;"},
	{"PDDATA",	0xF419, 1, 0x00, /* Port D Data Reg */
		{reg_get, pddata_put}, {0, 0}, {0, 0},
		"BB0:1;B1:1;B2:1;B3:1;B4:1;B5:1;B6:1;B7:1;"},
	{"PDPUEN",	0xF41A, 1, 0xff, /* Port D Pullup Enable Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"BB0:1;B1:1;B2:1;B3:1;B4:1;B5:1;B6:1;B7:1;"},
	{"PDPOL",	0xF41C, 1, 0x00, /* Port D Polarity Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"BB0:1;B1:1;B2:1;B3:1;B4:1;B5:1;B6:1;B7:1;"},
	{"PDIRQEN",	0xF41D, 1, 0x00, /* Port D IRQ Enable Reg */
		{reg_get, pdirqen_put}, {0, 0}, {0, 0},
		"BB0:1;B1:1;B2:1;B3:1;B4:1;B5:1;B6:1;B7:1;"},
	{"PDIRQEDGE",	0xF41F, 1, 0x00, /* Port D IRQ Edge Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"BB0:1;B1:1;B2:1;B3:1;B4:1;B5:1;B6:1;B7:1;"},

	{"PEDIR",	0xF420, 1, 0x00, /* Port E Direction Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"A:8;"},
	{"PEDATA",	0xF421, 1, 0x00, /* Port E Data Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"A:8;"},
	{"PEPUEN",	0xF422, 1, 0x80, /* X Port E Pullup Enable Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"A:8;"},
	{"PESEL",	0xF423, 1, 0x80, /* X Port E Select Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"A:8;"},

	{"PFDIR",	0xF428, 1, 0x00, /* Port F Direction Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"A:8;"},
	{"PFDATA",	0xF429, 1, 0x00, /* Port F Data Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"A:8;"},
	{"PFPUEN",	0xF42A, 1, 0xff, /* Port F Pullup Enable Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"A:8;"},
	{"PFSEL",	0xF42B, 1, 0xff, /* Port F Select Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"A:8;"},

	{"PGDIR",	0xF430, 1, 0x00, /* Port G Direction Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"UART_TXD:1;UART_RXD:1;PWMOUT:1;TOUT2:1;TIN2:1;TOUT1:1;TIN1:1;RTCOUT:1;"},
	{"PGDATA",	0xF431, 1, 0x00, /* Port G Data Reg */
		{reg_get, pgdata_put}, {0, 0}, {0, 0},
		"UART_TXD:1;UART_RXD:1;PWMOUT:1;TOUT2:1;TIN2:1;TOUT1:1;TIN1:1;RTCOUT:1;"},
	{"PGPUEN",	0xF432, 1, 0xff, /* Port G Pullup Enable Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"UART_TXD:1;UART_RXD:1;PWMOUT:1;TOUT2:1;TIN2:1;TOUT1:1;TIN1:1;RTCOUT:1;"},
	{"PGSEL",	0xF433, 1, 0xff, /* Port G Select Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"UART_TXD:1;UART_RXD:1;PWMOUT:1;TOUT2:1;TIN2:1;TOUT1:1;TIN1:1;RTCOUT:1;"},

	{"PJDIR",	0xF438, 1, 0x00, /* Port J Direction Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"A:8;"},
	{"PJDATA",	0xF439, 1, 0x00, /* Port J Data Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"A:8;"},
	{"PJSEL",	0xF43B, 1, 0x00, /* Port J Select Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"A:8;"},

	{"PKDIR",	0xF440, 1, 0x00, /* Port K Direction Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"SPIM_TXD:1;SPIM_RXD:1;SPIM_CLKO:1;SPIS_EN:1;SPIS_RXD:1;SPIS_CLKI:1;PCMCIA_CE2:1;PCMCIA_CE1:1;"},
	{"PKDATA",	0xF441, 1, 0x00, /* Port K Data Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"SPIM_TXD:1;SPIM_RXD:1;SPIM_CLKO:1;SPIS_EN:1;SPIS_RXD:1;SPIS_CLKI:1;PCMCIA_CE2:1;PCMCIA_CE1:1;"},
	{"PKPUEN",	0xF442, 1, 0x3f, /* Port K Pullup Enable Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"SPIM_TXD:1;SPIM_RXD:1;SPIM_CLKO:1;SPIS_EN:1;SPIS_RXD:1;SPIS_CLKI:1;PCMCIA_CE2:1;PCMCIA_CE1:1;"},
	{"PKSEL",	0xF443, 1, 0x3f, /* Port K Select Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"SPIM_TXD:1;SPIM_RXD:1;SPIM_CLKO:1;SPIS_EN:1;SPIS_RXD:1;SPIS_CLKI:1;PCMCIA_CE2:1;PCMCIA_CE1:1;"},

	{"PMDIR",	0xF448, 1, 0x00, /* Port M Direction Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"CTS:1;RTS:1;IRQ6:1;IRQ3:1;IRQ2:1;IRQ1:1;PEN_IRQ:1;UART_GPIO:1;"},
	{"PMDATA",	0xF449, 1, 0x00, /* Port M Data Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"CTS:1;RTS:1;IRQ6:1;IRQ3:1;IRQ2:1;IRQ1:1;PEN_IRQ:1;UART_GPIO:1;"},
	{"PMPUEN",	0xF44A, 1, 0xff, /* Port M Pullup Enable Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"CTS:1;RTS:1;IRQ6:1;IRQ3:1;IRQ2:1;IRQ1:1;PEN_IRQ:1;UART_GPIO:1;"},
	{"PMSEL",	0xF44B, 1, 0x02, /* Port M Select Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"CTS:1;RTS:1;IRQ6:1;IRQ3:1;IRQ2:1;IRQ1:1;PEN_IRQ:1;UART_GPIO:1;"},

	/* Pulse Width Modulator */
	{"PWMC",	0xF500, 2, 0x0000, /* PWM Control Reg */
		{pwmc_get_xxx, pwmc_put_xxx}, {reg_get, reg_put}, {0, 0},
		"CLKSEL:3;:1;PWMEN:1;POL:1;:1;PIN:1;LOAD:1;:5;IRQEN:1;PWMIRQ:1;"},
	{"PWMP",	0xF502, 2, 0x0000, /* PWM Period Reg */
		{0, 0}, {reg_get, reg_put}, {0, 0},
		"PERIOD:16;"},
	{"PWMW",	0xF504, 2, 0x0000, /* PWM Width Reg */
		{0, 0}, {reg_get, reg_put}, {0, 0},
		"WIDTH:16;"},
#if NOT_IMPL
	{"PWMCNT",	0xF506, 2, 0x0000, /* PWM Counter Reg */
		{0, 0}, {0, 0}, {0, 0},
		"COUNT:16;"},
#endif

	/* Timer */
	{"TCTL1",	0xF600, 2, 0x0000, /* Timer Unit 1 Control Reg */
		{0, 0}, {reg_get, reg_put}, {0, 0},
		"TEN:1;CLKSOURCE:3;IRQEN:1;OM:1;CAPTURE_EDGE:2;FRR:1;:7;"},
	{"TPRER1",	0xF602, 2, 0x0000, /* Timer Unit 1 Prescaler Reg */
		{0, 0}, {reg_get, reg_put}, {0, 0},
		"PRESCALE:8;:8;"},
	{"TCMP1",	0xF604, 2, 0xffff, /* Timer Unit 1 Compare Reg */
		{0, 0}, {reg_get, reg_put}, {0, 0},
		"COMPARE:16;"},
#if NOT_IMPL
	{"TCR1",	0xF606, 2, 0x0000, /* Timer Unit 1 Capture Reg */
		{0, 0}, {0, 0}, {0, 0},
		"CAPTURE:16;"},
#endif
	{"TCN1",	0xF608, 2, 0x0000, /* Timer Unit 1 Counter Reg */
		{0, 0}, {0, 0}, {0, 0},
		"COUNT:16;"},
	{"TSTAT1",	0xF60A, 2, 0x0000, /* Timer Unit 1 Status Reg */
		{0, 0}, {tstat1_get, tstat1_put}, {0, 0},
		"COMP:1;CAPT:1;:14;"},
	{"TCTL2",	0xF60C, 2, 0x0000, /* Timer Unit 2 Control Reg */
		{0, 0}, {reg_get, reg_put}, {0, 0},
		"TEN:1;CLKSOURCE:3;IRQEN:1;OM:1;CAPTURE_EDGE:2;FRR:1;:7;"},
	{"TPRER2",	0xF60E, 2, 0x0000, /* Timer Unit 2 Prescaler Reg */
		{0, 0}, {reg_get, reg_put}, {0, 0},
		"PRESCALE:8;:8;"},
	{"TCMP2",	0xF610, 2, 0xffff, /* Timer Unit 2 Compare Reg */
		{0, 0}, {reg_get, reg_put}, {0, 0},
		"COMPARE:16;"},
#if NOT_IMPL
	{"TCR2",	0xF612, 2, 0x0000, /* Timer Unit 1 Capture Reg */
		{0, 0}, {0, 0}, {0, 0},
		"CAPTURE:16;"},
#endif
	{"TCN2",	0xF614, 2, 0x0000, /* Timer Unit 2 Counter */
		{0, 0}, {0, 0}, {0, 0},
		"COUNT:16;"},
	{"TSTAT2",	0xF616, 2, 0x0000, /* Timer Unit 2 Status Reg */
		{0, 0}, {tstat2_get, tstat2_put}, {0, 0},
		"COMP:1;CAPT:1;:14;"},

	/* Watchdog */
	{"WCSR",	0xF618, 2, 0x0001, /* Watchdog Control and Status Reg */
		{0, 0}, {reg_get, reg_put}, {0, 0},
		"WDEN:1;FI:1;LOCK:1;WDRST:1;:12;"},
#if NOT_IMPL
	{"WRR",		0xF61A, 2, 0xffff, /* Watchdog Compare Reg */
		{0, 0}, {0, 0}, {0, 0},
		"COMPARE:16;"},
#endif
	{"WCN",		0xF61C, 2, 0x0000, /* Watchdog Counter */
		{0, 0}, {reg_get, wcn_put}, {0, 0},
		"COUNT:16;"},

	/* Serial Peripheral Interface Slave */
#if NOT_IMPL
	{"SPISR",	0xF700, 2, 0x0000, /* SPIS Reg */
		{0, 0}, {0, 0}, {0, 0},
		"DATA:8;SPIS_EN:1;POL:1;PHA:1;OVWR:1;DATA_RDY:1;EN_POL:1;IRQEN:1;SPISIRQ:1;"},
#endif

	/* Serial Peripheral Interface Master */
	{"SPIMDATA",	0xF800, 2, 0x0000, /* SPIM Data Reg */
		{0, 0}, {reg_get, reg_put}, {0, 0},
		"DATA:16;"},
	{"SPIMCONT",	0xF802, 2, 0x0000, /* SPIM Control/Status Reg */
		{0, 0}, {reg_get, spimcont_put}, {0, 0},
		"BITCOUNT:4;POL:1;PHA:1;IRQEN:1;SPIMIRQ:1;XCH:1;SPMEN:1;:3;DATARATE:3;"},

	/* UART - Universal Asynchronous Receiver/Transmitter */
	{"USTCNT",	0xF900, 2, 0x0000, /* UART Status/Control Reg */
		{0, 0}, {reg_get, ustcnt_put}, {0, 0},
		"TX_AVAIL_ENABLE:1;TX_HALF_ENABLE:1;TX_EMPTY_ENABLE:1;RX_READY_ENABLE:1;RX_HALF_ENABLE:1;RX_FULL_ENABLE:1;CTS_DELTA_ENABLE:1;GPIO_DELTA_ENABLE:1;BITS_8:1;STOP_BITS:1;ODD_EVEN:1;PARITY_ENABLE:1;RX_CLK_CONT:1;TX_ENABLE:1;RX_ENABLE:1;UART_ENABLE:1;"},
	{"UBAUD",	0xF902, 2, 0x003f, /* UART Baud Control Reg */
		{0, 0}, {reg_get, ubaud_put}, {0, 0},
		"PRESCALER:6;:2;DIVIDE:3;BAUD_SRC:1;GPIO_SRC:1;GPIO_DIR:1;GPIO:1;GPIO_DELTA:1;"},
	{"URX",		0xF904, 2, 0x0000, /* UART RX Reg */
		{urx_get_xxx, 0}, {urx_get, urx_put}, {0, 0},
		"DATA:8;PARITY_ERROR:1;BREAK:1;FRAME_ERROR:1;OVRUN:1;:1;DATA_READY:1;FIFO_HALF:1;FIFO_FULL:1;"},
	{"UTX",		0xF906, 2, 0x0000, /* UART TX Reg */
		{0, utx_put_xxx}, {utx_get, utx_put}, {0, 0},
		"DATA:8;CTS_DELTA:1;CTS_STATUS:1;:1;IGNORE_CTS:1;SEND_BREAK:1;TX_AVAIL:1;FIFO_HALF:1;FIFO_EMPTY:1;"},
	{"UMISC",	0xF908, 2, 0x0000, /* UART Misc Reg */
		{0, 0}, {reg_get, reg_put}, {0, 0},
		":2;TX_POL:1;RX_POL:1;IRDA_LOOP:1;IRDA_ENABLE:1;RTS:1;RTS_CONT:1;:4;LOOP:1;FORCE_PERR:1;CLK_SRC:1;:1;"},

	/* LCD Controller */
	{"LSSA",	0xFA00, 4, 0x00000000, /* Screen Starting Address Reg */
		{0, 0}, {0, 0}, {reg_get, lssa_put},
		"SSA:32;"},
	{"LVPW",	0xFA05, 1, 0xff, /* Virtual Page Width Reg */
		{reg_get, lvpw_put}, {0, 0}, {0, 0},
		"VPW:8;"},
	{"LXMAX",	0xFA08, 2, 0x03ff, /* Screen Width Reg */
		{0, 0}, {reg_get, reg_put}, {0, 0},
		"XMAX:10;:6;"},
	{"LYMAX",	0xFA0A, 2, 0x01ff, /* Screen Height Reg */
		{0, 0}, {reg_get, reg_put}, {0, 0},
		"YMAX:10;:6;"},
	{"LCXP",	0xFA18, 2, 0x0000, /* Cursor X Position */
		{0, 0}, {reg_get, reg_put}, {0, 0},
		"CXP:10;:4;CC:2;"},
	{"LCYP",	0xFA1A, 2, 0x0000, /* Cursor Y Position */
		{0, 0}, {reg_get, reg_put}, {0, 0},
		"CYP:10;:6;"},
	{"LCWCH",	0xFA1C, 2, 0x0101, /* Cursor Width & Height Reg */
		{0, 0}, {reg_get, reg_put}, {0, 0},
		"CH:5;:3;CW:5;:3;"},
	{"LBLKC",	0xFA1F, 1, 0x7f, /* Blink Control Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"BD:7;BKEN:1;"},
	{"LPICF",	0xFA20, 1, 0x00, /* Panel Interface Config Reg */
		{reg_get, lpicf_put}, {0, 0}, {0, 0},
		"GS:1;PBSIZ:2;:5;"},
#if NOT_IMPL
	{"LPOLCF",	0xFA21, 1, 0x00, /* Polarity Config Reg */
		{0, 0}, {0, 0}, {0, 0},
		"PIXPOL:1;LPPOL:1;FLMPOL:1;LCKPOL:1;:4;"},
	{"LACDRC",	0xFA23, 1, 0x00, /* ACD (M) Rate Control Reg */
		{0, 0}, {0, 0}, {0, 0},
		"ACD:4;:4;"},
#endif
	{"LPXCD",	0xFA25, 1, 0x00, /* Pixel Clock Divider Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"PCD:6;:2;"},
	{"LCKCON",	0xFA27, 1, 0x40, /* Clocking Control Reg */
		{reg_get, lckcon_put}, {0, 0}, {0, 0},
		"PCDS:1;DWIDTH:1;WS:4;DMA16:1;LCDCON:1;"},
	{"LLBAR",	0xFA29, 1, 0x3e, /* Last Buffer Address Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"LBAR:7;:1;"},
	{"LOTCR",	0xFA2B, 1, 0x3f, /* Octet Terminal Count Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"OTC:8;"},
	{"LPOSR",	0xFA2D, 1, 0x00, /* Panning Offset Reg */
		{reg_get, lposr_put}, {0, 0}, {0, 0},
		"POS:3;BOS:1;:4;"},
	{"LFRCM",	0xFA31, 1, 0xb9, /* Frame Rate Control Modulation Reg */
		{reg_get, reg_put}, {0, 0}, {0, 0},
		"YMOD:4;XMOD:4;"},
	{"LGPMR",	0xFA32, 2, 0x1073, /* Gray Palette Mapping Reg */
		{0, 0}, {reg_get, lgpmr_put}, {0, 0},
		"G2:4;G3:4;G0:4;G1:4;"},

	/* Real Time Clock */
	{"RTCHMS",	0xFB00, 4, 0x00000000, /* Hours Minutes Seconds Reg */
		{0, 0}, {0, 0}, {rhmsr_get, reg_put},
		"SECONDS:6;:10;MINUTES:6;:2;HOURS:5;:3;"},
	{"RTCALARM",	0xFB04, 4, 0x00000000, /* Alarm Reg */
		{0, 0}, {0, 0}, {reg_get, reg_put},
		"SECONDS:6;:10;MINUTES:6;:2;HOURS:5;:3;"},
	{"RTCCTL",	0xFB0C, 1, 0x00, /* Control Reg */
		{reg_get, reg_put}, {reg_get, rctl_put_xxx}, {0, 0},
		":5;REF384:1;:1;ENABLE:1;"},
	{"RTCISR",	0xFB0E, 1, 0x00, /* Interrupt Status Reg */
		{reg_get, risr_put}, {reg_get, risr_put_xxx}, {0, 0},
		"SW:1;MININT:1;ALARM:1;HOUR24:1;HZ1:1;:3;"},
	{"RTCIENR",	0xFB10, 1, 0x00, /* Interrupt Enable Reg */
		{reg_get, reg_put}, {reg_get, rienr_put_xxx}, {0, 0},
		"SW:1;MININT:1;ALARM:1;HOUR24:1;HZ1:1;:3;"},
#if NOT_IMPL
	{"STPWCH",	0xFB12, 1, 0x00, /* Interrupt Enable Reg */
		{0, 0}, {0, 0}, {0, 0},
		"COUNT:8;:8;"},
#endif

	{NULL}
};

/*---------------------------------------------------------------------------*
 * Main function
 *---------------------------------------------------------------------------*/

int
main(int argc, char *argv[])
{
	Fab	fab;

#ifdef WORDS_BIGENDIAN
	fab.bo = FAB_BIGENDIAN;
#else
	fab.bo = FAB_LITTLEENDIAN;
#endif
	fab.f_c = fopen("custom.c", "w");
	fab.lvl = 0;

	putln(&fab,
		"/*********************************************************\n"
 		" * WARNING: file is automatically generated do not modify\n"
		" *\n"
 		" * File:	custom.c (generated by fab_custom.c)\n"
		" *\n"
 		" * Abstract:	This code that simulates the dragonball's\n"
		" *		intelligent peripheral modules and system\n"
		" *		interface logic.\n"
		" *\n"
 		" * WARNING: file is automatically generated do not modify\n"
		" *********************************************************/\n"
		"\n");

	putln(&fab,
		"#include <ctype.h>\n"
		"#include <assert.h>\n"
		"#include <stdio.h>\n"
		"#include <time.h>\n"
		"#include <sys/types.h>\n"
		"#include <sys/time.h>\n"
		"#include <unistd.h>\n"
		"\n"
		"#include \"config.h\"\n"
		"#include \"sysdeps.h\"\n"
		"#include \"shared.h\"\n"
		"#include \"memory.h\"\n"
		"#include \"custom.h\"\n"
		"#include \"newcpu.h\"\n"
		"\n"
		"extern int sram_protect;\n"
		"\n");

	putln(&fab,
		"/* dragonball register locations */\n"
		"\n");
	gen_defs(&fab, dragonball);
	putln(&fab,
		"/*\n"
		" * Hmmm... We need to differentiate the debugger using the\n"
		" * UART from other programs (PPP, etc.) using it.  We check\n"
		" * the global variable dbgInDebugger (at address 0x110) to\n"
		" * see if we're in the debugger.\n"
		" *\n"
		" * - Ian\n"
		" */\n"
		"#define IN_DEBUGGER (get_byte(0x110))\n"
		"#define DEBUGGER_WRITING (CustShptr->gdb_writefd >= 0 && IN_DEBUGGER)\n"
		"#define DEBUGGER_READING (CustShptr->gdb_writefd >= 0 && IN_DEBUGGER)\n"
		"\n");

	putln(&fab,
		"/* dragonball register definitions */\n"
		"\n");
	gen_vars(&fab, dragonball);
	putln(&fab,
		"static shared_img *CustShptr = 0;\n"
		"\n"
		"static union {\n"
		"	UWORD	x;\n"
		"	struct {\n"
		"#ifdef WORDS_BIGENDIAN\n"
		"		unsigned FIFO_FULL	:1;\n"
		"		unsigned FIFO_HALF	:1;\n"
		"		unsigned DATA_READY	:1;\n"
		"		unsigned unused		:1;\n"
		"		unsigned OVRUN		:1;\n"
		"		unsigned FRAME_ERROR	:1;\n"
		"		unsigned BREAK		:1;\n"
		"		unsigned PARITY_ERROR	:1;\n"
		"		unsigned DATA		:8;\n"
		"#else /* not WORDS_BIGENDIAN */\n"
		"		unsigned DATA		:8;\n"
		"		unsigned PARITY_ERROR	:1;\n"
		"		unsigned BREAK		:1;\n"
		"		unsigned FRAME_ERROR	:1;\n"
		"		unsigned OVRUN		:1;\n"
		"		unsigned unused		:1;\n"
		"		unsigned DATA_READY	:1;\n"
		"		unsigned FIFO_HALF	:1;\n"
		"		unsigned FIFO_FULL	:1;\n"
		"#endif /* not WORDS_BIGENDIAN */\n"
		"	} anon;\n"
		"} db_URXdb;\n"
		"static UWORD	db_TSTAT1_lastseen;\n"
		"static UWORD	db_TSTAT2_lastseen;\n"
		"static UBYTE	db_PDDATA_edge;\n"
		"\n"
		"static unsigned long cycles;\n"
		"\n"
		"static int pendown = 0;\n"
		"static int penx;\n"
		"static int peny;\n"
		"\n"
		"/*\n"
		" * Exported variable\n"
		" */\n"
		"unsigned long specialflags;\n"
		"\n"
	);

	gen_init(&fab, dragonball);
	putln(&fab,
		"void\n"
		"customreset(void)\n"
		"{\n"
		"	cycles = 0;\n"
		"	specialflags = 0;\n"
		"\n"
		"	db_TSTAT1_lastseen = 0x0000;\n"
		"	db_TSTAT2_lastseen = 0x0000;\n"
		"	db_PDDATA_edge = 0x00;\n"
		"\n"
		"	db_URXdb.x = 0x0000;\n"
		"\n"
		"	db_reset();\n"
		"}\n"
		"\n");


	putln(&fab, HACK[0]);
	putln(&fab, "\n");

	gen_lget(&fab, dragonball);
	gen_lput(&fab, dragonball);
	gen_wget(&fab, dragonball);
	gen_wput(&fab, dragonball);
	gen_bget(&fab, dragonball);
	gen_bput(&fab, dragonball);

	putln(&fab,
		"addrbank custom_bank = {\n"
		"	custom_lget, custom_wget, custom_bget,\n"
		"	custom_lput, custom_wput, custom_bput,\n"
		"	default_xlate, default_check\n"
		"};\n"
		"\n");

	fclose(fab.f_c);
	return(0);
}