sead.s

一个专门针对mips的bootloader程序源代码

/************************************************************************
 *
 *  sead.S
 *
 *  SEAD specific initialisation
 *
 *  TBD : Move definitions to sead.h
 *
 *
 * ######################################################################
 *
 * Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved. 
 * 
 * Unpublished rights reserved under the Copyright Laws of the United States of 
 * America. 
 * 
 * This document contains information that is proprietary to MIPS Technologies, 
 * Inc. ("MIPS Technologies"). Any copying, modifying or use of this information 
 * (in whole or in part) which is not expressly permitted in writing by MIPS 
 * Technologies or a contractually-authorized third party is strictly 
 * prohibited. At a minimum, this information is protected under unfair 
 * competition laws and the expression of the information contained herein is 
 * protected under federal copyright laws. Violations thereof may result in 
 * criminal penalties and fines. 
 * MIPS Technologies or any contractually-authorized third party reserves the 
 * right to change the information contained in this document to improve 
 * function, design or otherwise. MIPS Technologies does not assume any 
 * liability arising out of the application or use of this information. Any 
 * license under patent rights or any other intellectual property rights owned 
 * by MIPS Technologies or third parties shall be conveyed by MIPS Technologies 
 * or any contractually-authorized third party in a separate license agreement 
 * between the parties. 
 * The information contained in this document constitutes one or more of the 
 * following: commercial computer software, commercial computer software 
 * documentation or other commercial items. If the user of this information, or 
 * any related documentation of any kind, including related technical data or 
 * manuals, is an agency, department, or other entity of the United States 
 * government ("Government"), the use, duplication, reproduction, release, 
 * modification, disclosure, or transfer of this information, or any related 
 * documentation of any kind, is restricted in accordance with Federal 
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal 
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use of 
 * this information by the Government is further restricted in accordance with 
 * the terms of the license agreement(s) and/or applicable contract terms and 
 * conditions covering this information from MIPS Technologies or any 
 * contractually-authorized third party. 
 *
 ************************************************************************/


/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <mips.h>
#include <init.h>
#include <sead.h>
#include <spd.h>
	
/************************************************************************
 *  Definitions
 ************************************************************************/

/* Assumptions (TBD) */
#define SEAD_MEMORY_SIZE		(32*1024*1024)
#define SEAD_MEMORY_BASE		SEAD_SYSTEMRAM_BASE

/* Worst case setup based on frequency assumptions */	
#define GCLK_SCALE_WORST_CASE		(SEAD_MAX_FREQ_MHZ * 10)
#define TREFRESH_WORST_CASE		(SEAD_MIN_FREQ_MHZ * 1000000 / 64020)
	
					
/************************************************************************
 *  Public variables
 ************************************************************************/

/************************************************************************
 *  Static variables
 ************************************************************************/

/************************************************************************
 *  Implementation : Public functions
 ************************************************************************/

	.set noreorder

LEAF(sys_init_sead)

	DISP_STR( msg_sead )
	b	  common_sead
	nop

END(sys_init_sead)

LEAF(sys_init_sead2)

	DISP_STR( msg_sead2 )
	b	  common_sead
	nop

END(sys_init_sead2)


/************************************************************************
 *  Implementation : Static functions
 ************************************************************************/

SLEAF(common_sead)

#define RA	t4

	/**** Store return address ****/
	move	RA, ra
	
	/**** Configure IIC controller ****/
	li	t0, KSEG1(SEAD_SD_SPDCNF)
#ifdef _SIMULATE_
	li	t1, 5
#else
	li	t1, GCLK_SCALE_WORST_CASE
#endif
	sw	t1, 0(t0)


	/**** Setup MRSCODE register based on SPD settings ****/

	/* Read CAS Latency */
	li	a0, SPD_CASLAT
	jal	read_eeprom
	nop

	/* v0 now contains CAS Latency support mask 
	 * If CAS latency 2 is supported, use this otherwise
	 * use CAS latency 3
	 */

	li	t0, SPD_CASLAT_2_BIT
	and	t0, v0
	bne	t0, zero, 1f
	li	v0, 2
	/* 2 not supported, so use 3 */
	li	v0, 3
1:	
	sll	v0, SEAD_SD_MRSCODE_CL_SHF

	/* Write MRSCODE */
	li	t0, KSEG1(SEAD_SD_MRSCODE)
	sw	v0, 0( t0 )


	/**** Setup CONFIG register based on SPD settings ****/

	/* Read number of DIMM banks */
	li	a0, SPD_MODULE_BANKS
	jal	read_eeprom
	nop	
	/* CSNUM = 2*number of DIMM banks */
	sll	v1, v0, 1
	sll	v1, SEAD_SD_CONFIG_CSN_SHF

	/* Read number of SDRAM banks */
	li	a0, SPD_DEVICE_BANKS
	jal	read_eeprom
	nop		
	sll	v0, SEAD_SD_CONFIG_BANKN_SHF
	or	v1, v0

	/* Read number of row address bits */
	li	a0, SPD_ROWS
	jal	read_eeprom
	nop
	li	t0, SPD_ROWS_B_MSK
	and	t1, v0, t0
	bne	t1, zero, config_error
	li	t0, SPD_ROWS_A_MSK
	and	v0, t0
	sll	v0, SEAD_SD_CONFIG_ROWW_SHF
	or	v1, v0

	/* Read number of column address bits */
	li	a0, SPD_COL
	jal	read_eeprom
	nop
	li	t0, SPD_COL_B_MSK
	and	t1, v0, t0
	bne	t1, zero, config_error
	li	t0, SPD_COL_A_MSK
	and	v0, t0
	sll	v0, SEAD_SD_CONFIG_COLW_SHF
	or	v1, v0	
	
	/* Check that CONFIG is for a 32 MByte module */
	/* (BANKN,CSN) must equal (2,4) or (4,2) */
	andi	v0, v1, SEAD_SD_CONFIG_BANKN_MSK
	srl	v0, SEAD_SD_CONFIG_BANKN_SHF
	li	t1, 2
	beq	v0, t1, 4f
	nop
	li	t1, 4
	beq	v0, t1, 2f
	nop
	b	config_error
	nop

4:
	andi	v0, v1, SEAD_SD_CONFIG_CSN_MSK
	srl	v0, SEAD_SD_CONFIG_CSN_SHF
	li	t1, 4
	bne	v0, t1, config_error
	nop
	b	csnbankn_done
	nop
	
2:
	li	t0, ~SEAD_SD_CONFIG_CSN_MSK
	and	v1, t0
	ori	v1, 2 << SEAD_SD_CONFIG_CSN_SHF



csnbankn_done:	

	/* (ROWW,COLW) must equal (11,9) or (12,8) after adjustment */
	andi	v0, v1, SEAD_SD_CONFIG_ROWW_MSK
	srl	v0, SEAD_SD_CONFIG_ROWW_SHF
	li	t1, 11
	beq	v0, t1, 9f
	nop
	li	t1, 12
	beq	v0, t1, 8f
	nop
	b	config_error
	nop

9:
	andi	v0, v1, SEAD_SD_CONFIG_COLW_MSK
	srl	v0, SEAD_SD_CONFIG_COLW_SHF
	li	t1, 9
	blt	v0, t1, config_error
	li	t0, ~SEAD_SD_CONFIG_COLW_MSK
	and	v1, t0
	b	colrow_done	
	ori	v1, 9 << SEAD_SD_CONFIG_COLW_SHF

8:
	andi	v0, v1, SEAD_SD_CONFIG_COLW_MSK
	srl	v0, SEAD_SD_CONFIG_COLW_SHF
	li	t1, 8
	blt	v0, t1, config_error
	li	t0, ~SEAD_SD_CONFIG_COLW_MSK
	and	v1, t0
	ori	v1, 8 << SEAD_SD_CONFIG_COLW_SHF

colrow_done:	


	/* Write CONFIG */
	li	t0, KSEG1(SEAD_SD_CONFIG)
	sw	v1, 0(t0)



	/**** Setup LATENCIES register based on SPD settings ****/

	/*  We assume 100MHz 
	 *  Since we assume 100MHz, we must divide the values 
	 *  read from the eeprom (number of ns) with 10.
	 *  We divide by 8 since this is easier (TBD). Result
	 *  is too conservative !
	 */
	
	/* Read Minimum Row Precarge time */
	li	a0, SPD_MRPT
	jal	read_eeprom	
	nop
	srl	v0, 3	/* x/8 */
	/* Values 2..4 supported */
	li	t0, 2
	subu	t0, t0, v0
	bltz	t0, 1f
	nop
	li	v0, 2 /* Set to min value */
1:		
	li	t0, 4
	subu	t0, v0, t0
	bltz	t0, 1f
	nop
	li	v0, 4 /* Set to max value */
1:	
	sll	v1, v0, SEAD_SD_LATENCIES_TRP_SHF

	/* Read Minimum RAS Pulse Width */
	li	a0, SPD_MRPW
	jal	read_eeprom	
	nop
	srl	v0, 3	/* x/8 */
	/* Values 2..8 supported */
	li	t0, 2
	subu	t0, t0, v0
	bltz	t0, 1f
	nop
	li	v0, 2 /* Set to min value */
1:		
	li	t0, 8
	subu	t0, v0, t0
	bltz	t0, 1f
	nop
	li	v0, 8 /* Set to max value */
1:	
	sll	v0, SEAD_SD_LATENCIES_TRAS_SHF
	or	v1, v0

	/* Read RAS to CAS Defay Min */
	li	a0, SPD_RCDM
	jal	read_eeprom	
	nop
	srl	v0, 3	/* x/8 */
	/* Values 2..3 supported */
	li	t0, 2
	subu	t0, t0, v0
	bltz	t0, 1f
	nop
	li	v0, 2 /* Set to min value */
1:		
	li	t0, 3
	subu	t0, v0, t0
	bltz	t0, 1f
	nop
	li	v0, 3 /* Set to max value */
1:	
	sll	v0, SEAD_SD_LATENCIES_TRCD_SHF
	or	v1, v0	

	/* TDPL is set to 2 */
	li	v0, 2 << SEAD_SD_LATENCIES_TDPL_SHF
	or	v1, v0
	
	/* Write LATENCIES */	
	li	t0, KSEG1(SEAD_SD_LATENCIES)
	sw	v1, 0(t0)


	/**** Setup TREFRESH register ****/	
	li	t0, KSEG1(SEAD_SD_TREFRESH)
	li	v0, TREFRESH_WORST_CASE
	sw	v0, 0(t0)

	
	/**** Activate the SDRAM controller ****/
	li	t0, KSEG1(SEAD_SD_REGSSET)
	li	t1, SEAD_SD_REGSSET_SET_BIT
	sw	t1, 0(t0)			

	
	/**** Setup return parameters ****/
	li	v1, SEAD_MEMORY_SIZE

done:	
	/**** Return ****/
	jr	RA
	move	v0, zero

read_eeprom:	

	DISP_STR( msg_spd )
	
	/* Setup address */
	li	t9, KSEG1(SEAD_SD_SPDADR)
	sw	a0, 0(t9)	

	/* Poll for ready */
	li	t9, KSEG1(SEAD_SD_SPDDAT)
	li	t8, SEAD_SD_SPDDAT_BUSY_BIT
1:
	lw	v0, 0(t9)
	and	a0, v0, t8
	bne	a0, zero, 1b
	nop

	/* Check read err flag */
	li	t8, SEAD_SD_SPDDAT_READ_ERR_BIT
	and	a0, v0, t8
	beq	a0, zero, eeprom_done
	nop

	/* Error */
	jr	RA
	li	v0, ERROR_SPD

	/* Done */

eeprom_done:

	DISP_STR( msg_sead )
			
	li	t9, SEAD_SD_SPDDAT_RDATA_MSK
	jr	ra
	and	v0, t9


config_error:
	jr	RA
	li	v0, ERROR_SDRAM_CONFIG


END(common_sead)


/* Messages */

	.text
	
MSG( msg_sead,  "SEAD" )
MSG( msg_sead2, "SEAD-2" )
MSG( msg_spd,   "SPD" )