📄 syscon_cpu.c
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/************************************************************************
* cpu_tlb_count_rm5261_read
************************************************************************/
static UINT32
cpu_tlb_count_rm5261_read(
void *param,
void *data )
{
*(UINT8 *)param = QED_RM5261_TLB_ENTRIES;
return OK;
}
/************************************************************************
* Implementation : Public functions
************************************************************************/
/************************************************************************
*
* syscon_arch_cpu_init
* Description :
* -------------
*
* Initialize cpu specific part of SYSCON
*
* Return values :
* ---------------
*
* None
*
************************************************************************/
void
syscon_arch_cpu_init(
t_syscon_obj *objects ) /* Array of SYSCON objects */
{
UINT32 mask;
syscon_objects = objects;
/* Detect whether cache/TLB is configurable */
/* This feature is present specifically to support configuration
* testing of the core in a lead vehicle, and is not supported
* in any other environment. Attempting to use this feature
* outside of the scope of a lead vehicle is a violation of the
* MIPS Architecture, and may cause unpredictable operation of
* the processor.
*/
switch( sys_processor )
{
case AU1XXX:
/* Au1000 does not support configurable cache */
config1_init = CP0_config1_read();
cache_configurable = FALSE;
mmu_configurable = FALSE;
tlb_avail = TRUE;
break;
case MIPS_4Kc :
case MIPS_4Kmp :
case MIPS_5Kc :
/* Store initial setting of CP0 CONFIG1 register */
config1_init = CP0_config1_read();
mask = sys_cpu_configurability();
cache_configurable =
(mask & SYS_CPU_CONFIGURABILITY_CACHE) ? TRUE : FALSE;
mmu_configurable =
(mask & SYS_CPU_CONFIGURABILITY_MMU) ? TRUE : FALSE;
tlb_avail =
( REGFIELD( CP0_config_read(), C0_CONFIG_MT ) ==
C0_CONFIG_MT_TLB ) ? TRUE : FALSE;
break;
default :
cache_configurable = FALSE;
mmu_configurable = FALSE;
tlb_avail = TRUE;
break;
}
/* Register objects */
syscon_register_id_cpu( SYSCON_CPU_CYCLE_PER_COUNT_ID,
/* 4Kc */
cpu_cycle_per_count_4Kc_read, NULL,
NULL, NULL,
/* 4Km */
cpu_cycle_per_count_4Km_read, NULL,
NULL, NULL,
/* 5Kc */
cpu_cycle_per_count_5Kc_read, NULL,
NULL, NULL,
/* QED RM5261 */
cpu_cycle_per_count_qed_rm5261_read, NULL,
NULL, NULL,
/* Au1000 */
cpu_cycle_per_count_Au1000_read, NULL,
NULL, NULL );
syscon_register_id_cpu( SYSCON_CPU_CP0_CONFIG1_ID,
/* 4Kc */
cpu_cp0_config1_mips32_read, NULL,
NULL, NULL,
/* 4Km */
cpu_cp0_config1_mips32_read, NULL,
NULL, NULL,
/* 5Kc */
cpu_cp0_config1_mips32_read, NULL,
NULL, NULL,
/* QED RM5261 */
NULL, NULL,
NULL, NULL,
/* Au1000 */
cpu_cp0_config1_mips32_read, NULL,
NULL, NULL );
syscon_register_id_cpu( SYSCON_CPU_CP0_CONFIG1_RESET_ID,
/* 4Kc */
cpu_cp0_config1_reset_mips32_read, NULL,
NULL, NULL,
/* 4Km */
cpu_cp0_config1_reset_mips32_read, NULL,
NULL, NULL,
/* 5Kc */
cpu_cp0_config1_reset_mips32_read, NULL,
NULL, NULL,
/* QED RM5261 */
NULL, NULL,
NULL, NULL,
/* Au1000 */
cpu_cp0_config1_reset_mips32_read, NULL,
NULL, NULL );
syscon_register_id_cpu( SYSCON_CPU_CP0_DEBUG_ID,
/* 4Kc */
cpu_cp0_debug_mips32_read, NULL,
cpu_cp0_debug_mips32_write, NULL,
/* 4Km */
cpu_cp0_debug_mips32_read, NULL,
cpu_cp0_debug_mips32_write, NULL,
/* 5Kc */
cpu_cp0_debug_mips32_read, NULL,
cpu_cp0_debug_mips32_write, NULL,
/* QED RM5261 */
NULL, NULL,
NULL, NULL,
/* Au1000 */
cpu_cp0_debug_mips32_read, NULL,
cpu_cp0_debug_mips32_write, NULL );
syscon_register_id_cpu( SYSCON_CPU_CP0_DEPC_ID,
/* 4Kc */
cpu_cp0_depc_mips32_read, NULL,
cpu_cp0_depc_mips32_write, NULL,
/* 4Km */
cpu_cp0_depc_mips32_read, NULL,
cpu_cp0_depc_mips32_write, NULL,
/* 5Kc */
cpu_cp0_depc_mips32_read, NULL,
cpu_cp0_depc_mips32_write, NULL,
/* QED RM5261 */
NULL, NULL,
NULL, NULL,
/* Au1000 */
cpu_cp0_depc_mips32_read, NULL,
cpu_cp0_depc_mips32_write, NULL );
syscon_register_id_cpu( SYSCON_CPU_CP0_PERFCOUNT_ID,
/* 4Kc */
cpu_cp0_perfcount_mips32_read, NULL,
cpu_cp0_perfcount_mips32_write, NULL,
/* 4Km */
cpu_cp0_perfcount_mips32_read, NULL,
cpu_cp0_perfcount_mips32_write, NULL,
/* 5Kc */
cpu_cp0_perfcount_mips32_read, NULL,
cpu_cp0_perfcount_mips32_write, NULL,
/* QED RM5261 */
NULL, NULL,
NULL, NULL,
/* Au1000 */
cpu_cp0_perfcount_mips32_read, NULL,
cpu_cp0_perfcount_mips32_write, NULL );
syscon_register_id_cpu( SYSCON_CPU_TLB_COUNT_ID,
/* 4Kc */
cpu_tlb_count_mips32_read, NULL,
NULL, NULL,
/* 4Km */
cpu_tlb_count_mips32_read, NULL,
NULL, NULL,
/* 5Kc */
cpu_tlb_count_mips32_read, NULL,
NULL, NULL,
/* QED RM5261 */
cpu_tlb_count_rm5261_read, NULL,
NULL, NULL,
/* Au1000 */
cpu_tlb_count_mips32_read, NULL,
NULL, NULL );
syscon_register_generic( SYSCON_CPU_TLB_COUNT_RESET_ID,
syscon_uint8_read, (void *)&tlb_reset,
NULL, NULL );
syscon_register_generic( SYSCON_CPU_TLB_AVAIL_ID,
syscon_bool_read, (void *)&tlb_avail,
syscon_bool_write, (void *)&tlb_avail );
syscon_register_generic( SYSCON_CPU_ICACHE_AVAIL_BPW_ID,
cpu_icache_avail_bpw_generic_read, NULL,
NULL, NULL );
syscon_register_generic( SYSCON_CPU_DCACHE_AVAIL_BPW_ID,
cpu_dcache_avail_bpw_generic_read, NULL,
NULL, NULL );
syscon_register_generic( SYSCON_CPU_ICACHE_AVAIL_ASSOC_ID,
cpu_icache_avail_assoc_generic_read, NULL,
NULL, NULL );
syscon_register_generic( SYSCON_CPU_DCACHE_AVAIL_ASSOC_ID,
cpu_dcache_avail_assoc_generic_read, NULL,
NULL, NULL );
syscon_register_generic( SYSCON_CPU_CACHE_CONFIGURABLE_ID,
cpu_cache_configurable_generic_read, NULL,
NULL, NULL );
syscon_register_generic( SYSCON_CPU_MMU_CONFIGURABLE_ID,
cpu_mmu_configurable_generic_read, NULL,
NULL, NULL );
/* Determine initial TLB entry count */
if( tlb_avail )
{
SYSCON_read( SYSCON_CPU_TLB_COUNT_ID,
(void *)&tlb_reset,
sizeof(UINT8) );
}
else
{
tlb_reset = 0;
}
}
/************************************************************************
*
* syscon_register_id_cpu
* Description :
* -------------
*
* Function used to register CPU specific SYSCON object functions.
*
* A read and/or write function may be registered for each cpu.
* A NULL function pointer indicates that the operation (read or
* write) is not allowed for the particular cpu.
*
* read_data and write_data pointers are passed to the read and write
* function.
* Return values :
* ---------------
*
* None
*
************************************************************************/
void
syscon_register_id_cpu(
t_syscon_ids id, /* OBJECT ID from syscon_api.h */
t_syscon_func read_4Kc, /* 4Kc read function */
void *read_data_4Kc, /* Registered data */
t_syscon_func write_4Kc, /* 4Kc write function */
void *write_data_4Kc, /* Registered data */
t_syscon_func read_4Km, /* 4Km read function */
void *read_data_4Km, /* Registered data */
t_syscon_func write_4Km, /* 4Km write function */
void *write_data_4Km, /* Registered data */
t_syscon_func read_5Kc, /* 5Kc read function */
void *read_data_5Kc, /* Registered data */
t_syscon_func write_5Kc, /* 5Kc write function */
void *write_data_5Kc, /* Registered data */
t_syscon_func read_qed_rm5261, /* QED RM5261 read function */
void *read_data_qed_rm5261, /* Registered data */
t_syscon_func write_qed_rm5261, /* QED RM5261 write function */
void *write_data_qed_rm5261, /* Registered data */
t_syscon_func read_Au1000, /* Au1000 read function */
void *read_data_Au1000, /* Registered data */
t_syscon_func write_Au1000, /* Au1000 write function */
void *write_data_Au1000) /* Registered data */
{
t_syscon_obj *obj;
obj = &syscon_objects[id];
switch( sys_processor )
{
case AU1XXX :
obj->read = read_Au1000;
obj->read_data = read_data_Au1000;
obj->write = write_Au1000;
obj->write_data = write_data_Au1000;
break;
case MIPS_4Kc :
obj->read = read_4Kc;
obj->read_data = read_data_4Kc;
obj->write = write_4Kc;
obj->write_data = write_data_4Kc;
break;
case MIPS_4Kmp :
obj->read = read_4Km;
obj->read_data = read_data_4Km;
obj->write = write_4Km;
obj->write_data = write_data_4Km;
break;
case MIPS_5Kc :
obj->read = read_5Kc;
obj->read_data = read_data_5Kc;
obj->write = write_5Kc;
obj->write_data = write_data_5Kc;
break;
case QED_RM52XX :
obj->read = read_qed_rm5261;
obj->read_data = read_data_qed_rm5261;
obj->write = write_qed_rm5261;
obj->write_data = write_data_qed_rm5261;
break;
default : /* Should not happen */
obj->read = NULL;
obj->write = NULL;
break;
}
}
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