syscon_cpu.c

一个专门针对mips的bootloader程序源代码

/************************************************************************
 *
 *  syscon_cpu.c
 *
 *  CPU specific parts of SYSCON module
 *
 *
 * ######################################################################
 *
 * Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved. 
 * 
 * Unpublished rights reserved under the Copyright Laws of the United States of 
 * America. 
 * 
 * This document contains information that is proprietary to MIPS Technologies, 
 * Inc. ("MIPS Technologies"). Any copying, modifying or use of this information 
 * (in whole or in part) which is not expressly permitted in writing by MIPS 
 * Technologies or a contractually-authorized third party is strictly 
 * prohibited. At a minimum, this information is protected under unfair 
 * competition laws and the expression of the information contained herein is 
 * protected under federal copyright laws. Violations thereof may result in 
 * criminal penalties and fines. 
 * MIPS Technologies or any contractually-authorized third party reserves the 
 * right to change the information contained in this document to improve 
 * function, design or otherwise. MIPS Technologies does not assume any 
 * liability arising out of the application or use of this information. Any 
 * license under patent rights or any other intellectual property rights owned 
 * by MIPS Technologies or third parties shall be conveyed by MIPS Technologies 
 * or any contractually-authorized third party in a separate license agreement 
 * between the parties. 
 * The information contained in this document constitutes one or more of the 
 * following: commercial computer software, commercial computer software 
 * documentation or other commercial items. If the user of this information, or 
 * any related documentation of any kind, including related technical data or 
 * manuals, is an agency, department, or other entity of the United States 
 * government ("Government"), the use, duplication, reproduction, release, 
 * modification, disclosure, or transfer of this information, or any related 
 * documentation of any kind, is restricted in accordance with Federal 
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal 
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use of 
 * this information by the Government is further restricted in accordance with 
 * the terms of the license agreement(s) and/or applicable contract terms and 
 * conditions covering this information from MIPS Technologies or any 
 * contractually-authorized third party. 
 *
 ************************************************************************/


/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <sys_api.h>
#include <syscon_api.h>
#include <syscon.h>
#include <mips.h>

#include <mips4Kc.h>
#include <qed_rm52xx.h>
#include <pb1000.h>

/************************************************************************
 *  Definitions
 ************************************************************************/

/************************************************************************
 *  Public variables
 ************************************************************************/

/************************************************************************
 *  Static variables
 ************************************************************************/

/* Reset value of CONFIG1 register */
static UINT32 config1_init;

/* Cache/MMU configurability, availability */
static bool   cache_configurable;
static bool   mmu_configurable;
static bool   tlb_avail;
static UINT8  tlb_reset;

/* Pointer to array of SYSCON objects */
static t_syscon_obj       *syscon_objects;

/************************************************************************
 *  Static function prototypes
 ************************************************************************/


/************************************************************************
 *  Implementation : Static functions registered for handling particular 
 *  SYSCON objects for particular platform(s)
 ************************************************************************/


/************************************************************************
 *  cpu_cp0_config1_reset_mips32_read
 ************************************************************************/
static UINT32
cpu_cp0_config1_reset_mips32_read(
    void *param,
    void *data )
{
    *(UINT32 *)param = config1_init;
    return OK;
}


/************************************************************************
 *  cpu_cycle_per_count_4Kc_read
 ************************************************************************/
static UINT32
cpu_cycle_per_count_4Kc_read(
    void *param,
    void *data )
{
    *(UINT32 *)param = MIPS4KC_COUNT_CLK_PER_CYCLE; 
    return OK;
}

/************************************************************************
*  cpu_cycle_per_count_Au1000_read
************************************************************************/
static UINT32
cpu_cycle_per_count_Au1000_read(
							 void *param,
							 void *data )
{

	*(UINT32 *)param = 1; //AU1000_COUNT_CLK_PER_CYCLE; 
    return OK;
}


/************************************************************************
 *  cpu_cycle_per_count_4Km_read
 ************************************************************************/
static UINT32
cpu_cycle_per_count_4Km_read(
    void *param,
    void *data )
{
    /* 4Km and 4Kp */
    *(UINT32 *)param = MIPS4KC_COUNT_CLK_PER_CYCLE; 
    return OK;
}


/************************************************************************
 *  cpu_cycle_per_count_5Kc_read
 ************************************************************************/
static UINT32
cpu_cycle_per_count_5Kc_read(
    void *param,
    void *data )
{
    /* TBD : Check this */
    *(UINT32 *)param = MIPS4KC_COUNT_CLK_PER_CYCLE; 
    return OK;
}


/************************************************************************
 *  cpu_cycle_per_count_qed_rm5261_read
 ************************************************************************/
static UINT32
cpu_cycle_per_count_qed_rm5261_read(
    void *param,
    void *data )
{
    *(UINT32 *)param = QED_RM5261_COUNT_CLK_PER_CYCLE; 
    return OK;
}


/************************************************************************
 *  cpu_icache_avail_bpw_generic_read
 ************************************************************************/
static UINT32
cpu_icache_avail_bpw_generic_read(
    void *param,
    void *data )
{ 
    sys_cpu_cache_bpw( TRUE, (t_sys_array *)param );
    return OK;
}


/************************************************************************
 *  cpu_dcache_avail_bpw_generic_read
 ************************************************************************/
static UINT32
cpu_dcache_avail_bpw_generic_read(
    void *param,
    void *data )
{
    sys_cpu_cache_bpw( FALSE, (t_sys_array *)param );
    return OK;
}


/************************************************************************
 *  cpu_icache_avail_assoc_generic_read
 ************************************************************************/
static UINT32
cpu_icache_avail_assoc_generic_read(
    void *param,
    void *data )
{
    sys_cpu_cache_assoc( TRUE, (t_sys_array *)param );
    return OK;
}


/************************************************************************
 *  cpu_dcache_avail_assoc_generic_read
 ************************************************************************/
static UINT32
cpu_dcache_avail_assoc_generic_read(
    void *param,
    void *data )
{
    sys_cpu_cache_assoc( FALSE, (t_sys_array *)param );
    return OK;
}


/************************************************************************
 *  cpu_cache_configurable_generic_read
 ************************************************************************/
static UINT32
cpu_cache_configurable_generic_read(
    void *param,
    void *data )
{
    *(bool *)param = cache_configurable;
    return OK;
}


/************************************************************************
 *  cpu_mmu_configurable_generic_read
 ************************************************************************/
static UINT32
cpu_mmu_configurable_generic_read(
    void *param,
    void *data )
{
    *(bool *)param = mmu_configurable;
    return OK;
}


/************************************************************************
 *  cpu_cp0_config1_mips32_read
 ************************************************************************/
static UINT32
cpu_cp0_config1_mips32_read(
    void *param,
    void *data )
{
    *(UINT32*)param = CP0_config1_read();
    return OK;
}


/************************************************************************
 *  cpu_cp0_debug_mips32_read
 ************************************************************************/
static UINT32
cpu_cp0_debug_mips32_read(
    void *param,
    void *data )
{
    *(UINT32 *)param = CP0_debug_read();
    return OK;
}


/************************************************************************
 *  cpu_cp0_debug_mips32_write
 ************************************************************************/
static UINT32
cpu_cp0_debug_mips32_write(
    void *param,
    void *data )
{
    CP0_debug_write( *(UINT32 *)param );
    return OK;
}


/************************************************************************
 *  cpu_cp0_depc_mips32_read
 ************************************************************************/
static UINT32
cpu_cp0_depc_mips32_read(
    void *param,
    void *data )
{
    *(UINT32 *)param = CP0_depc_read();
    return OK;
}


/************************************************************************
 *  cpu_cp0_depc_mips32_write
 ************************************************************************/
static UINT32
cpu_cp0_depc_mips32_write(
    void *param,
    void *data )
{
    CP0_depc_write( *(UINT32 *)param );
    return OK;
}


/************************************************************************
 *  cpu_cp0_perfcount_mips32_read
 ************************************************************************/
static UINT32
cpu_cp0_perfcount_mips32_read(
    void *param,
    void *data )
{
    *(UINT32 *)param = CP0_perfcount_read();
    return OK;
}


/************************************************************************
 *  cpu_cp0_perfcount_mips32_write
 ************************************************************************/
static UINT32
cpu_cp0_perfcount_mips32_write(
    void *param,
    void *data )
{
    CP0_perfcount_write( *(UINT32 *)param );
    return OK;
}

/************************************************************************
 *  cpu_tlb_count_mips32_read
 ************************************************************************/
static UINT32
cpu_tlb_count_mips32_read(
    void *param,
    void *data )
{
    *(UINT8 *)param = REGFIELD( CP0_config1_read(), C0_CONFIG1_MMUSIZE ) + 1;
    return OK;
}