sys_cpu_s.s

一个专门针对mips的bootloader程序源代码

	li	t1, C0_CONFIG1_DS_SHF
	sllv	t1, s0, t1
	or	t0, t1

	li	t1, C0_CONFIG1_DL_SHF
	sllv	t1, s1, t1
	or	t0, t1

	li	t1, C0_CONFIG1_DA_SHF
	sllv	t1, s2, t1
	or	t0, t1

	/* Write CONFIG1 register */
	MTC0_SEL_OPCODE( 8, 16, C0_CONFIG1_SEL )   /* t0 = $8 */

	/* Disable write access to config1 */
	MTC0(	s5, C0_CONFIG )

	/* Empty pipeline */
	nop; nop; nop; nop; nop; nop

	/* Restore CP0 STATUS */
	MTC0(   s4, C0_STATUS )

	/* Return */
	lw	ra, 0(sp)
	lw	s0, 4(sp)
	lw	s1, 8(sp)
	lw	s2, 12(sp)
	lw	s3, 16(sp)
	lw	s4, 20(sp)
	lw	s5, 24(sp)
	lw	s6, 28(sp)

	jr	ra
	addiu	sp, 8*4
	
END( sys_cpu_dcache_config )
		


/************************************************************************
 *
 *                          sys_cpu_mmu_config
 *  Description :
 *  -------------
 *
 *  Configure MMU
 *
 *  a0 holds the required setting of Config0[8]
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
LEAF( sys_cpu_mmu_config )

	/* Disable interrupts (store old value of CP0 STATUS) */
	MFC0(   t0, C0_STATUS )
	li	t1, ~C0_STATUS_IE_MSK
	and	t1, t0, t1
	MTC0(   t1, C0_STATUS )

	/* Enable write access to Config0[8] */
	MFC0(   t1, C0_CONFIG )
	li	t2, C0_CONFIG_WC_BIT
	or	t1, t1, t2
	MTC0(	t1, C0_CONFIG )

	/* Set bit 8 */
	li	t2, ~(1 << 8)
	and	t1, t2
	sll	a0, 8
	or	t1, a0
	MTC0(   t1, C0_CONFIG )

	/* Disable write access to Config1[8] */
	li	t2, ~C0_CONFIG_WC_BIT
	and	t1, t2
	MTC0(   t1, C0_CONFIG )	

	/* Empty pipeline */
	nop; nop; nop; nop; nop; nop

	/* Restore CP0 STATUS */
	MTC0(   t0, C0_STATUS )

	/* Return */
	jr	ra
	nop
		
END( sys_cpu_mmu_config )



/************************************************************************
 *
 *                          sys_cpu_configurability
 *  Description :
 *  -------------
 *
 *  Determine cpu configurability
 *
 *  This feature is present specifically to support configuration
 *  testing of the core in a lead vehicle, and is not supported
 *  in any other environment.  Attempting to use this feature
 *  outside of the scope of a lead vehicle is a violation of the
 *  MIPS Architecture, and may cause unpredictable operation of
 *  the processor.
 *
 *  Return values :
 *  ---------------
 *
 *  v0 = mask with the following bit definitions :
 *
 *  Bit 0 : Set if MMU may be configured (TLD -> Fixed)
 *  Bit 1 : Set if cache may be downsized
 *
 ************************************************************************/
LEAF( sys_cpu_configurability )

	/* Reserve space on stack */
	addiu	sp, -2*4

	/* Store return address */
	sw	ra, 0(sp)

	/* Disable interrupts (store old value of CP0 STATUS) */
	MFC0(   t0, C0_STATUS )
	sw	t0, 4(sp)
	li	t1, ~C0_STATUS_IE_MSK
	and	t1, t0, t1
	MTC0(   t1, C0_STATUS )
		
	/* Shift to uncached */
	la	t0, sys_cpu_configurability_uncached
	KSEG1A( t0)
	jr	t0
	nop

sys_cpu_configurability_uncached:

	/* Set default = Not configurable */
	move    v0, zero

	/* Check that Config0[WC] bit is cleared */
	MFC0(   t1, C0_CONFIG )
	li	t2, C0_CONFIG_WC_BIT
	and	t3, t1, t2
	bne	t3, zero, done
	nop

	/* Set Config0[WC] bit */
	or      t1, t2
	MTC0(   t1, C0_CONFIG )

	/* Check Config0[8] : MMU configurability */
	li	t2, (1 << 8)
	and	t3, t1, t2
	bne	t3, zero, 1f
	nop
	/*  Config0[8] == 0 => TLB.
	 *  Try to set bit and read it back.
	 */
	or	t3, t1, t2
	MTC0(   t3, C0_CONFIG )
	MFC0(   t3, C0_CONFIG )
	and	t3, t3, t2
	beq	t3, zero, 1f
	nop
	/*  Bit was set, so MMU may be configured.
	 *  Clear bit and set mask.
	 */	
	MTC0(   t1, C0_CONFIG )
	ori	v0, 1

1:
	/* Determine cache configurability
	 *
	 * Read CONFIG1 register, which holds implementation data
	 * t9 = $25, CONFIG1 = $16 
	 */
	MFC0_SEL_OPCODE( 25, 16, C0_CONFIG1_SEL )     
#define config1	t9

	/*  Check IL (I-cache line size) field.
	 *  If 0, there is no (I)cache.
	 */
	li      t2, C0_CONFIG1_IL_MSK
	and	t3, t9, t2
	beq	t3, zero, done
	nop

	/* Try to clear IL and read it back */
	li      t2, ~C0_CONFIG1_IL_MSK
	and	t3, t9, t2
	MTC0_SEL_OPCODE( 11, 16, C0_CONFIG1_SEL )  /* t3 = $11 */
	MFC0_SEL_OPCODE( 11, 16, C0_CONFIG1_SEL )     
	li	t2, C0_CONFIG1_IL_MSK
	and	t3, t2
	bne	t3, zero, done
	nop
	/*  IL was cleared, so CACHE may be configured.
	 *  Restore setting and set mask.
	 */
	MTC0_SEL_OPCODE( 25, 16, C0_CONFIG1_SEL )
	ori     v0, 2

done:
	/* Clear WC bit */
	li	t2, ~C0_CONFIG_WC_BIT	
	and	t1, t2
	MFC0(   t1, C0_CONFIG )

	/***** Reinitialise I-cache *****/

	/* a1 := line size (bytes) */
	la      a1, sys_icache_linesize
	lw	a1, 0(a1)

	/* a0 := cache size (bytes) */
	la      a0, sys_icache_lines
	lw	a0, 0(a0)
	multu	a0, a1
	MFLO(   a0 )

	/* Initialise */
	la	t0, sys_init_icache
	KSEG1A( t0)		/* Make it uncached */
	jal	t0
	nop
	
	/* Restore CP0 STATUS */
	lw	t0, 4(sp)
	MTC0(   t0, C0_STATUS )

	/* Return */
	lw	ra, 0(sp)
	jr	ra
	addiu	sp, 2*4

END( sys_cpu_configurability )
	

/************************************************************************	
 *
 *                          sys_cpu_type
 *  Description :
 *  -------------
 *
 *  Determine whether processor is 32 or 64 bit.
 *
 *  Parameters :
 *  ------------
 *
 *  None
 *
 *  Return values :
 *  ---------------
 *
 *  v0 = 0 -> 32 bit
 *  v0 = 1 -> 64 bit
 *
 ************************************************************************/
LEAF(sys_cpu_type)

	/* Determine processor */
	MFC0(   t0, C0_PRID)
	li	t1, C0_PRID_PRID_MSK | C0_PRID_COMP_MSK
	and     t0, t1

	/* Check if it is a MIPS32/64 processor */	
	li      t1, C0_PRID_COMP_MSK
	and	t1, t0
	srl	t1, C0_PRID_COMP_SHF
	li	t2, C0_PRID_COMP_NOT_MIPS32_64
	bne	t1, t2, mips32_64
	nop
	/* Not a MIPS32/64 processor */
	li	t1, QED_RM52XX
	bne	t1, t0, sys_cpu_type_done   /* Should not happen    */
	move	v0, zero		    /* 32 bit default	    */
	b	sys_cpu_type_done
	li	v0, 1			    /* QED RM52XX is 64 bit */

mips32_64:
	/* Determine 32/64 based on AT field of CONFIG register */
	MFC0(   t0, C0_CONFIG )
	li	t1, C0_CONFIG_AT_MSK
	and	t0, t1
	srl	t0, C0_CONFIG_AT_SHF
	li	t1, C0_CONFIG_AT_MIPS32
	beq	t0, t1, sys_cpu_type_done
	move	v0, zero
	li	v0, 1

sys_cpu_type_done :
        jr	ra
	nop

END(sys_cpu_type)

				
/************************************************************************
 *  Implementation : Static functions
 ************************************************************************/