sys_cpu_s.s

一个专门针对mips的bootloader程序源代码

/************************************************************************
 *
 *  sys_cpu_s.S
 *
 *  cpu functions
 *
 *
 * ######################################################################
 *
 * Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved. 
 * 
 * Unpublished rights reserved under the Copyright Laws of the United States of 
 * America. 
 * 
 * This document contains information that is proprietary to MIPS Technologies, 
 * Inc. ("MIPS Technologies"). Any copying, modifying or use of this information 
 * (in whole or in part) which is not expressly permitted in writing by MIPS 
 * Technologies or a contractually-authorized third party is strictly 
 * prohibited. At a minimum, this information is protected under unfair 
 * competition laws and the expression of the information contained herein is 
 * protected under federal copyright laws. Violations thereof may result in 
 * criminal penalties and fines. 
 * MIPS Technologies or any contractually-authorized third party reserves the 
 * right to change the information contained in this document to improve 
 * function, design or otherwise. MIPS Technologies does not assume any 
 * liability arising out of the application or use of this information. Any 
 * license under patent rights or any other intellectual property rights owned 
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 * or any contractually-authorized third party in a separate license agreement 
 * between the parties. 
 * The information contained in this document constitutes one or more of the 
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 * documentation of any kind, is restricted in accordance with Federal 
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 * Acquisition Regulation Supplement 227.7202 for military agencies. The use of 
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 *
 ************************************************************************/


/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <sys_api.h>
#include <mips.h>

/************************************************************************
 *  Definitions
 ************************************************************************/

/************************************************************************
 *  Public variables
 ************************************************************************/

/************************************************************************
 *  Static variables
 ************************************************************************/

/************************************************************************
 *  Implementation : Public functions
 ************************************************************************/

	.set noreorder
			
/************************************************************************
 *
 *                          sys_cpu_icache_config
 *  Description :
 *  -------------
 *
 *  Configure icache
 *
 *  a0 holds the requested sets per way field
 *  a1 holds the requested line size (0 or hardware default) field
 *  a2 holds the requested associativity field
 *  a3 holds the reset value of CONFIG1
 *	
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
LEAF( sys_cpu_icache_config )

	/* Reserve space on stack */
	addiu	sp, -8*4

	/* Store return address, s0..s4 */
	sw	ra, 0(sp)
	sw	s0, 4(sp)
	sw	s1, 8(sp)
	sw	s2, 12(sp)
	sw	s3, 16(sp)
	sw	s4, 20(sp)
	sw	s5, 24(sp)
	sw	s6, 28(sp)

	/* Copy registers to preserved registers */
	move	s0, a0
	move	s1, a1
	move	s2, a2
	move	s3, a3
	MFC0(   s4, C0_STATUS )
	MFC0(   s5, C0_CONFIG )
	MFC0_SEL_OPCODE( 22, 16, C0_CONFIG1_SEL )     /* s6 = $22 */

	/* Disable interrupts */
	li	t0, ~C0_STATUS_IE_MSK
	and	t0, s4, t0
	MTC0(   t0, C0_STATUS )
	
	/* Shift to uncached */
	la	t0, sys_cpu_icache_config_uncached
	KSEG1A( t0)
	jr	t0
	nop

sys_cpu_icache_config_uncached :
			       
	/* Enable write access to config1 */
	li	t0, C0_CONFIG_WC_BIT
	or	t0, s5, t0
	MTC0(	t0, C0_CONFIG )

	/* Set Icache settings to reset values */
	li	t0, (C0_CONFIG1_IS_MSK | C0_CONFIG1_IL_MSK | C0_CONFIG1_IA_MSK)
	and	t0, s3, t0
	li	t1, ~(C0_CONFIG1_IS_MSK | C0_CONFIG1_IL_MSK | C0_CONFIG1_IA_MSK)
	and	t1, s6, t1
	or	t1, t0

	/* Write CONFIG1 register */
	MTC0_SEL_OPCODE( 9, 16, C0_CONFIG1_SEL )   /* t1 = $9 */

	/* Empty pipeline */
	nop; nop; nop; nop; nop; nop

	/* Prepare for initialising cache */
	
	/* a1 := line size (bytes) */
	la      a1, sys_icache_linesize
	lw	a1, 0(a1)

	/* a0 := cache size (bytes) */
	la      a0, sys_icache_lines
	lw	a0, 0(a0)
	multu	a0, a1
	MFLO(   a0 )

	/* Initialise */
	la	t0, sys_init_icache
	KSEG1A( t0)		/* Make it uncached */
	jal	t0
	nop

	/* Set Icache settings to requested values */
	li	t0, ~(C0_CONFIG1_IS_MSK | C0_CONFIG1_IL_MSK | C0_CONFIG1_IA_MSK)
	and	t0, s6, t0

	li	t1, C0_CONFIG1_IS_SHF
	sllv	t1, s0, t1
	or	t0, t1

	li	t1, C0_CONFIG1_IL_SHF
	sllv	t1, s1, t1
	or	t0, t1

	li	t1, C0_CONFIG1_IA_SHF
	sllv	t1, s2, t1
	or	t0, t1

	/* Write CONFIG1 register */
	MTC0_SEL_OPCODE( 8, 16, C0_CONFIG1_SEL )    /* t0 = $8 */

	/* Disable write access to config1 */
	MTC0(	s5, C0_CONFIG )

	/* Empty pipeline */
	nop; nop; nop; nop; nop; nop

	/* Restore CP0 STATUS */
	MTC0(   s4, C0_STATUS )

	/* Return */
	lw	ra, 0(sp)
	lw	s0, 4(sp)
	lw	s1, 8(sp)
	lw	s2, 12(sp)
	lw	s3, 16(sp)
	lw	s4, 20(sp)
	lw	s5, 24(sp)
	lw	s6, 28(sp)

	jr	ra
	addiu	sp, 8*4

END( sys_cpu_icache_config )


		
/************************************************************************
 *
 *                          sys_cpu_dcache_config
 *  Description :
 *  -------------
 *
 *  Configure dcache
 *
 *  a0 holds the requested sets per way field
 *  a1 holds the requested line size (0 or hardware default) field
 *  a2 holds the requested associativity field
 *  a3 holds the reset value of CONFIG1
 *	
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
LEAF( sys_cpu_dcache_config )

	/* Reserve space on stack */
	addiu	sp, -8*4

	sw	ra, 0(sp)
	sw	s0, 4(sp)
	sw	s1, 8(sp)
	sw	s2, 12(sp)
	sw	s3, 16(sp)
	sw	s4, 20(sp)
	sw	s5, 24(sp)
	sw	s6, 28(sp)

	/* Copy registers to preserved registers */
	move	s0, a0
	move	s1, a1
	move	s2, a2
	move	s3, a3
	MFC0(   s4, C0_STATUS )
	MFC0(   s5, C0_CONFIG )
	MFC0_SEL_OPCODE( 22, 16, C0_CONFIG1_SEL )     /* s6 = $22 */
	
	/* Disable interrupts */
	li	t0, ~C0_STATUS_IE_MSK
	and	t0, s4, t0
	MTC0(   t0, C0_STATUS )
		
	/* Flush D-Cache */
	addiu	sp, -4*4
	la      t0, sys_dcache_flush_all
	jal	t0
	nop
	addiu	sp, 4*4

	/* Shift to uncached */
	la	t0, sys_cpu_dcache_config_uncached
	KSEG1A( t0)
	jr	t0
	nop

sys_cpu_dcache_config_uncached :

	/* Enable write access to config1 */
	li	t0, C0_CONFIG_WC_BIT
	or	t0, s5, t0
	MTC0(	t0, C0_CONFIG )

	/* Set Dcache settings to reset values */
	li	t0, (C0_CONFIG1_DS_MSK | C0_CONFIG1_DL_MSK | C0_CONFIG1_DA_MSK)
	and	t1, s3, t0
	li	t0, ~(C0_CONFIG1_DS_MSK | C0_CONFIG1_DL_MSK | C0_CONFIG1_DA_MSK)
	and	t2, s6, t0
	or	t2, t1

	/* Write CONFIG1 register */
	MTC0_SEL_OPCODE( 10, 16, C0_CONFIG1_SEL )  /* t2 = $10 */

	/* Empty pipeline */
	nop; nop; nop; nop; nop; nop

	/* Prepare for initialising cache */

	/* a1 := line size (bytes) */
	la      a1, sys_icache_linesize
	lw	a1, 0(a1)

	/* a0 := cache size (bytes) */
	la      a0, sys_icache_lines
	lw	a0, 0(a0)
	multu	a0, a1
	MFLO(   a0 )

	/* Initialise */
	la	t0, sys_init_icache
	KSEG1A( t0)		/* Make it uncached */
	jal	t0
	nop
	
	/* Set Dcache settings to requested values */
	li	t0, ~(C0_CONFIG1_DS_MSK | C0_CONFIG1_DL_MSK | C0_CONFIG1_DA_MSK)
	and	t0, s6, t0