sys_cpu.c

一个专门针对mips的bootloader程序源代码

/************************************************************************
 *
 *  sys_cpu.c
 *
 *  CPU specific configuration
 *
 *
 * ######################################################################
 *
 * Copyright (c) 1999-2000 MIPS Technologies, Inc. All rights reserved. 
 * 
 * Unpublished rights reserved under the Copyright Laws of the United States of 
 * America. 
 * 
 * This document contains information that is proprietary to MIPS Technologies, 
 * Inc. ("MIPS Technologies"). Any copying, modifying or use of this information 
 * (in whole or in part) which is not expressly permitted in writing by MIPS 
 * Technologies or a contractually-authorized third party is strictly 
 * prohibited. At a minimum, this information is protected under unfair 
 * competition laws and the expression of the information contained herein is 
 * protected under federal copyright laws. Violations thereof may result in 
 * criminal penalties and fines. 
 * MIPS Technologies or any contractually-authorized third party reserves the 
 * right to change the information contained in this document to improve 
 * function, design or otherwise. MIPS Technologies does not assume any 
 * liability arising out of the application or use of this information. Any 
 * license under patent rights or any other intellectual property rights owned 
 * by MIPS Technologies or third parties shall be conveyed by MIPS Technologies 
 * or any contractually-authorized third party in a separate license agreement 
 * between the parties. 
 * The information contained in this document constitutes one or more of the 
 * following: commercial computer software, commercial computer software 
 * documentation or other commercial items. If the user of this information, or 
 * any related documentation of any kind, including related technical data or 
 * manuals, is an agency, department, or other entity of the United States 
 * government ("Government"), the use, duplication, reproduction, release, 
 * modification, disclosure, or transfer of this information, or any related 
 * documentation of any kind, is restricted in accordance with Federal 
 * Acquisition Regulation 12.212 for civilian agencies and Defense Federal 
 * Acquisition Regulation Supplement 227.7202 for military agencies. The use of 
 * this information by the Government is further restricted in accordance with 
 * the terms of the license agreement(s) and/or applicable contract terms and 
 * conditions covering this information from MIPS Technologies or any 
 * contractually-authorized third party. 
 *
 ************************************************************************/


/************************************************************************
 *  Include files
 ************************************************************************/

#include <sysdefs.h>
#include <syscon_api.h>
#include <sys_api.h>
#include <mips.h>

/************************************************************************
 *  Definitions
 ************************************************************************/

/************************************************************************
 *  Public variables
 ************************************************************************/

/************************************************************************
 *  Static variables
 ************************************************************************/

static char *name_mips      = MIPS_NAME;

static char *name_4Kc	    = "MIPS 4Kc";
static char *name_4Kmp	    = "MIPS 4Km/4Kp";
static char *name_5Kc	    = "MIPS 5Kc";
static char *name_qed52xx   = "QED RM5261"; /* Assume 5261 */
static char *name_Au1000	= "Alchemy Au1000";
static char *name_Au1100	= "Alchemy Au1100";
static char *name_Au1500	= "Alchemy Au1500";

#define BPW_SETTINGS	8
static UINT32 bpw[BPW_SETTINGS];

#define ASSOC_SETTINGS	8
static UINT32 assoc[ASSOC_SETTINGS];


/************************************************************************
 *  Static function prototypes
 ************************************************************************/

/************************************************************************
 *  Implementation : Public functions
 ************************************************************************/


/************************************************************************
 *
 *                          sys_decode_procid
 *  Description :
 *  -------------
 *
 *  Map processor ID field to string hodling the name of the CPU
 *  
 *  Return values :
 *  ---------------
 *
 *  String holding name of CPU
 *
 ************************************************************************/
char *
sys_decode_procid( void )
{
	UINT32 prid = CP0_prid_read();
    switch( sys_processor )
    {
		
	case AU1XXX:
		switch (prid & 0xFF000000)
		{
			case 0x00000000: return name_Au1000; break;
			case 0x01000000: return name_Au1500; break;
			case 0x02000000: return name_Au1100; break;
			default:
				return name_Au1000; break;
		}
		break;
      case MIPS_4Kc :
        return name_4Kc;
        break;
      case MIPS_4Kmp :
        return name_4Kmp;
	break;
      case MIPS_5Kc :
        return name_5Kc;
	break;
      case QED_RM52XX :
        return name_qed52xx;
	break;
      default :
        return NULL;
    }
}


/************************************************************************
 *
 *                          sys_cpu_config
 *  Description :
 *  -------------
 *
 *  Configure CPU cache/mmu settings
 *
 *  This feature is present specifically to support configuration
 *  testing of the core in a lead vehicle, and is not supported
 *  in any other environment.  Attempting to use this feature
 *  outside of the scope of a lead vehicle is a violation of the
 *  MIPS Architecture, and may cause unpredictable operation of
 *  the processor.
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
void
sys_cpu_config( 
    bool	       icache,
    bool	       dcache,
    bool	       mmu,
    t_sys_cpu_decoded  *setting )
{
    UINT32 config1, config1_reset, l, s;
    bool   cache_configurable, mmu_configurable;
    
    SYSCON_read( SYSCON_CPU_CACHE_CONFIGURABLE_ID,
		 &cache_configurable,
		 sizeof(bool) );

    SYSCON_read( SYSCON_CPU_MMU_CONFIGURABLE_ID,
		 &mmu_configurable,
		 sizeof(bool) );

    if( mmu_configurable && mmu )
    {
        sys_cpu_mmu_config( setting->mmu_tlb ? 0 : 1 );

	SYSCON_write( SYSCON_CPU_TLB_AVAIL_ID,
		      (void *)&setting->mmu_tlb,
		      sizeof( bool ) );
    }

    if( cache_configurable )
    {
        SYSCON_read( SYSCON_CPU_CP0_CONFIG1_ID,
                     &config1,
	             sizeof(UINT32) );

        SYSCON_read( SYSCON_CPU_CP0_CONFIG1_RESET_ID,
                     &config1_reset,
	             sizeof(UINT32) );

        if( icache )
        {
	    if( setting->i_bpw == 0 )
	    {
	        l = 0;
	        s = REGFIELD( config1_reset, C0_CONFIG1_IS );
	    }
	    else
	    {
	        l = REGFIELD( config1_reset, C0_CONFIG1_IL );

	        for( s = 0;
	             CACHE_CALC_SPW(s) != setting->i_bpw / CACHE_CALC_LS(l);
	             s++ );
	    }

            sys_cpu_icache_config( s, l, setting->i_assoc - 1, config1_reset );
        }

        if( dcache )
        {
	    if( setting->d_bpw == 0 )
	    {
	        l = 0;
	        s = REGFIELD( config1_reset, C0_CONFIG1_DS );
	    }
	    else
	    {
	        l = REGFIELD( config1_reset, C0_CONFIG1_DL );

	        for( s = 0;
	             CACHE_CALC_SPW(s) != setting->d_bpw / CACHE_CALC_LS(l);
	             s++ );
	    }

            sys_cpu_dcache_config( s, l, setting->d_assoc - 1, config1_reset );
        }
    }
}


/************************************************************************
 *                          sys_cpu_cache_bpw
 ************************************************************************/
void
sys_cpu_cache_bpw(
    bool         icache,	/* TRUE -> icache, FALSE -> dcache	*/
    t_sys_array  *sys_array )
{
    UINT32 spw, linesize;

    sys_array->array = bpw;

    /* Calc number of sets (lines) per way and determine linesize */      
    if( icache )
    {
        spw      = sys_icache_lines / sys_icache_assoc;
        linesize = sys_icache_linesize;
    }
    else
    {
        spw      = sys_dcache_lines / sys_dcache_assoc;
        linesize = sys_dcache_linesize;
    }

    switch( sys_processor )
    {

      case MIPS_4Kc :
      case MIPS_4Kmp :
      case MIPS_5Kc :

	 /* Init count of valid settings */
         sys_array->count = 0;

	 /*  Sets per way may be 64,128,256,512,1024,2048,4096.
	  *  Available spw are calculated by starting with the
	  *  hardware default and stepping down.
	  *  The check on count should not be necessary.
	  */
	 while( (spw >= 64) && (sys_array->count < BPW_SETTINGS - 1) )
	 {
	     bpw[sys_array->count] = spw * linesize;  /* Calc bytes per way */
	     sys_array->count++;
	     spw >>= 1;
         }

	 /* 0 bytes per way is also possible by setting line size to 0 */
	 bpw[sys_array->count] = 0;
	 sys_array->count++;

	 break;

	case AU1XXX :
	
      default :
         /* Not possible to configure cache size */
	 bpw[0]		  = spw * linesize;
         sys_array->count = 1;
	 break;
    }
}


/************************************************************************
 *                          sys_cpu_cache_assoc
 ************************************************************************/
void
sys_cpu_cache_assoc(
    bool         icache,	/* TRUE -> icache, FALSE -> dcache	*/
    t_sys_array  *sys_array )
{
    UINT32 max;
    UINT32 i;
    UINT32 index;
    
    sys_array->array = assoc;

    /* Determine max associativity */      
    max = icache ? sys_icache_assoc : sys_dcache_assoc;

    switch( sys_processor )
    {
      case MIPS_4Kc :
      case MIPS_4Kmp :
      case MIPS_5Kc :

	/*  Valid way counts are 1..max. 
	 *  The MIN macro is not really necessary.
	 */
	for( index = 0, i = MIN( ASSOC_SETTINGS, max );
	     index < MIN( ASSOC_SETTINGS, max );
	     index++, i-- )
        {
	    assoc[index] = i;
	}
   
	sys_array->count = max;

	break;
	case AU1XXX :	

      default :
        /* Not possible to configure cache size */
	assoc[0] = max;
        sys_array->count = 1;
	break;
    }
}


/************************************************************************
 *
 *                          sys_decode_compid
 *  Description :
 *  -------------
 *
 *  Map Company ID field of CPO PrId register to string with company name.
 *
 *  Return values :
 *  ---------------
 *
 *  None
 *
 ************************************************************************/
char *
sys_decode_compid( 
    UINT8 compid )	/* Company ID field of CP0 PRId register	*/
{
    switch( compid )
    {
      case C0_PRID_COMP_MIPS :
        return name_mips;
	break;
      default :
        return NULL;
	break;
    }
}


/************************************************************************
 *  Implementation : Static functions
 ************************************************************************/