stage1_init.s

来自「一个非常有用的nand_flash的boot程序代码」· S 代码 · 共 582 行 · 第 1/2 页

  Tcsh=0110
Tcsoff=110
   Twp=000110
  Tcsw=0000
   Tpm=0100
    Ta=010011
 */
#ifdef EB
#define MEM_STCFG0	0x002D0243 /* 16-bit big-endian */
#endif
#ifdef EL
#define MEM_STCFG0	0x002D0043 /* 16-bit little-endian */
#endif
#define MEM_STTIME0	0x06618113
#define MEM_STADDR0	0x11803E00

/* RCE1: NAND (default to x8 Toshiba Flash) */
#define MEM_STCFG1	0x00440045 // fix!!! double-check w/ au1550
#define MEM_STTIME1	0x00007774 // fix!!! double-check w/ au1550
#define MEM_STADDR1	0x02000FFF // fix!!! not enabled

/* RCE2:   CPLD, LAN91C111, IDE PIOmode4, SRAM

 Tcsoe=MAX( 0ns,      20ns,         25ns,  0ns) = (1+4  clocks) AS=1
 Toecs=MAX( 0ns,       5ns,         10ns,  0ns) = (1+1  clocks) AH=1
  Twcs=MAX( 0ns,       5ns,         10ns,  0ns) = (1+1  clocks)
  Tcsh=MAX(10ns,      20ns,         25ns,  0ns) = (1+4  clocks)
Tcsoff=MAX(10ns,      20ns,         25ns,  0ns) = (1+4  clocks)
   Twp=MAX(15ns,      20ns,         70ns, 50ns) = (1+13 clocks)
  Tcsw=MAX(10ns,      20ns,         20ns,  0ns) = (1+3  clocks)
   Tpm=MAX( 0ns,       0ns,       25/0ns,  0ns) = (1+0  clocks)
    Ta=MAX( 5ns,      35ns,         95ns, 80ns) = (1+18 clocks)

mem_stcfg2: 1000 0110 0010 1101 0000 0000 1100 0110 : 0x862D00C6 
Tcsoe=100 (see above)
Toecs=001 (see above)
   AH=1   (hold needed)
   NW=0   (n/a)
   AS=1   (setup needed)
    S=0   (asynchronous)
   DE=1   (de-assert)
 MBSa=1
  MBC=0
   TA=1   (Tcsh for reads and writes)
   BE=0   (little endian)
   TS=0   (asynchronous operation)
   EW=1   (absolutely needed)
 MBSb=1
   BS=0   (n/a)
   PM=0   (disable page mode)
   RO=0   (writable)
  DTY=6   (IDE)

mem_sttime2: 0001 0100 0100 0011 0100 1100 0001 0010 : 0x14434C12
  Twcs=001
  Tcsh=0100
Tcsoff=100
   Twp=001101
  Tcsw=0011
   Tpm=0000
    Ta=010010
*/
#define MEM_STCFG2	0x862D00C6
#define MEM_STTIME2	0x14434C12
#define MEM_STADDR2	0x10C03f00

/* RCE3: PCMCIA 250ns */
#define MEM_STCFG3	0x00040042
#define MEM_STTIME3	0x280E3E07
#define MEM_STADDR3	0x10000000

#define MEM_SDCONFIGA_E 0x80000000	//this does not match the databook
#define MEM_SDCONFIGB_BB (1<<19)
#define MEM_SDCONFIGB_BA (1<<7)

/*
 * SDCS0 - 64MB Micron MT46V16M16TG-5B (4Mbit x 16 x 4bank x 2devices)
 * SDCS1 - 64MB Micron MT46V16M16TG-5B (4Mbit x 16 x 4bank x 2devices)

With a DDR clock of 198MHz (sdconfigb[CR]=1), DDR clock period is 5ns

mem_sdmode: 0000 0001 0010 0111 0010 0010 0010 0100 : 0x01272224
  Twtr=001  (1+1 clocks) data sheet specs 2 clocks for tWTR
   Twr=010  (1+2 clocks) data sheet specs 15ns for tWR
  Tras=0111 (1+7 clocks) data sheet specs 40ns for tRAS
   Trp=010  (1+2 clocks) data sheet specs 15ns for tRP
Trcdwr=010  (1+2 clocks) data sheet specs 15ns for tRCD
Trcdrd=010  (1+2 clocks) data sheet specs 15ns for tRCD
  Tcas=100  (CL=3      ) data sheet specs CL=3 for 133mhz < tCLK <= 200mhz

mem_sdaddr: 0010 0010 0001 0000 0000 0011 1111 0000 : 0x221003F0
    BR=0    (bank,row,col)
    RS=10   (13 row)
    CS=010  (9 col)
	 E=1    (enabled)
  CSBA=0000000000 (0x00000000)
CSMASK=1111110000 (0xFC000000)

mem_sdconfiga: 0011 0000 1101 0000 0000 0110 0000 1010 : 0x30D0060A
     E=0    (refresh disable)
    CE=11   (both clocks enabled)
   RPT=00   (1 refresh per cycle)
   Trc=1101 (1+13 clocks) data sheet specs 55ns for tRC, 70ns for tRFC
   REF=0x60A (1562 clocks) data sheet specs 7.8125us intervals (8K rows in 64ms)

mem_sdconfigb: 1000 0000 0000 0010 0000 0000 0000 0000 : 0x8002000C
    CR=1    (1:1)
    BW=0    (32bit wide bus)
    MT=0    (DDR1)
  PSEL=0    (addr 10 for auto precharge)
    C2=0    (core lowest priority)
    AC=00   (default)
    HP=0    (no half-pll mode)
    PM=00   (no power modes)
CKECNT=00   (n/a)
    BB=0    (normal)
    DS=1    (full drive strength)
    FS=0    (normal)
   PDX=00   (n/a)
CKEmin=00   (n/a ?)
    CB=0    (normal)
 TXARD=000  (n/a)
    BA=0    (no block)
  TXSR=001100 (1+12 * 16=208 > 200 clocks)

mem_sdwrmd: 0000 0000 0011 0010 : 0x0032
 mode=000000 normal operation
   CL=011   CL=3
   BT=0     sequential burst type
   BL=010   burst length of 4
 */
#define MEM_SDMODE0_DDR		0x01272224
#define MEM_SDMODE1_DDR		0x01272224
#define MEM_SDADDR0_DDR		0x221003F0 
#define MEM_SDADDR1_DDR		0x221043F0
#define MEM_SDCONFIGA_DDR	0x30D0060A
#define MEM_SDCONFIGB_DDR	0x8002000C
#define MEM_SDWRMD0_DDR		0x00000032
#define MEM_SDWRMD1_DDR		0x00000032

#define MEM_1MS			((396000000/1000000) * 1000)

/*
 * Board CPLD registers
 */
#define PB1200_BCSR_ADDR	0xAD800000

#define bcsr_whoami			0x00 /* 1010=Pb1200-DDR1, 1011=Pb1200-DDR2 */
#define bcsr_status			0x04
#define bcsr_switches		0x08
#define bcsr_resets			0x0C
#define bcsr_pcmcia			0x10
#define bcsr_board			0x14
#define bcsr_leds			0x18
#define bcsr_system			0x1C
#define bcsr_icer			0x20
#define bcsr_iser			0x24
#define bcsr_icmr			0x28
#define bcsr_ismr			0x2C
#define bcsr_ssr			0x30
#define bcsr_isr			0x34

/*
 * Uncomment the following to place SRAM (instead of DDR) at 0x00000000
 * This creates the following:
 * 0x00000000 for 64M : RCE2, with SRAM @ 0x00000000
 * 0x04000000 for 64M : DDR rank1 (DDR rank0 is disabled)
 * NOTE: Must also change YAMON/arch/include/pb1000.h to match.
 */
//#define USE_SRAM
#ifdef USE_SRAM
#undef MEM_STADDR2
#define MEM_STADDR2	0x10003f00
#undef MEM_SDADDR0_DDR
#define MEM_SDADDR0_DDR 0x00000000
#undef PB1200_BCSR_ADDR
#define PB1200_BCSR_ADDR  0xA1800000
#endif

/********************************************************************/
/********************************************************************/
/********************************************************************/
/********************************************************************/


	.section ".stage1"
	.set noreorder
	.set mips32

	.globl stage1
stage1:
	// Change core to litle endian
#	li		t0, AU1200_SYS_ADDR
#	li		t1, 1
#	sw		t1, sys_endian(t0)
#	sync
#	mfc0	t2, CP0_Config
#	mtc0	t2, CP0_Config
#	nop

	// Step 10) Establish CPU PLL frequency
#	li		t0, AU1200_SYS_ADDR
#	li		t1, SYS_CPUPLL
#	sw		t1, sys_cpupll(t0)
#	nop	

	
	// Step 11) Establish system bus divider
	li		t1, SYS_POWERCTRL
	sw		t1, sys_powerctrl(t0)
	sync

	li	v0, 5
	sw	v0,0(a0)
	sync	
		
	   
	// Load cacheable space start address
	la v1, run_cache
	
	// Cache remainder of first page
#	cache 0x14, 0x060(t8)		                   
	cache 0x14, 0x080(t8)		                   
	cache 0x14, 0x0a0(t8)		  
	cache 0x14, 0x0c0(t8)		                   
	cache 0x14, 0x0e0(t8)		                   
	cache 0x14, 0x100(t8)		                   
	cache 0x14, 0x120(t8)		                   
	cache 0x14, 0x140(t8)		                   
	cache 0x14, 0x160(t8)		            
	cache 0x14, 0x180(t8)		            
	cache 0x14, 0x1a0(t8)		            
	cache 0x14, 0x1c0(t8)		            
	cache 0x14, 0x1e0(t8)		


	jr v1	// run from cacheable space
	nop
	nop

 run_cache:

	// wait 1mS before setup
	li		t1, MEM_1MS
1:	add		t1, -1
	bne		t1, zero, 1b
	nop

	li		t0, AU1200_MEM_ADDR

	li		t1, MEM_SDCONFIGA_DDR
	li		t2, MEM_SDCONFIGB_DDR
	li		t3, MEM_SDCONFIGB_BB
	or		t2, t2, t3 /* block LCD/MAE during init */
	sw		t1, mem_sdconfiga(t0)
	sw		t2, mem_sdconfigb(t0)

	li		t1, MEM_SDMODE0_DDR
	sw		t1, mem_sdmode0(t0)

	li		t1, MEM_SDADDR0_DDR
	sw		t1, mem_sdaddr0(t0)

	// Micron specific: Set normal (not reduced) drive strength 
	lw		t1, mem_sdconfigb(t0)
	li		t2, MEM_SDCONFIGB_BA
	or		t1, t2, t1
	sw		t1, mem_sdconfigb(t0)

	/* PRECHARGE ALL */
	sw		zero, mem_sdprecmd(t0)

	/* LOAD MODE REGISTER extended mode register */
	li		t1, 0x40000000
	sw		t1, mem_sdwrmd0(t0)		
	sync

	la		sp,__stacktop
	addiu	sp,sp,-4

	// Load Nand Boot Image
	jal		load_stage2
	nop
	
	// Jump to the boot stage2 reset code
	la		t0, reset
	jalr	t0
	nop