stage1_init.s

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/*********************************************************************
 *
 * Copyright:
 *	Advanced Micro Devices, AMD. All Rights Reserved.  
 *  You are hereby granted a copyright license to use, modify, and
 *  distribute the SOFTWARE so long as this entire notice is
 *  retained without alteration in any modified and/or redistributed
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 *  as such. No licenses are granted by implication, estoppel or
 *  otherwise under any patents or trademarks of AMD. This 
 *  software is provided on an "AS IS" basis and without warranty.
 *
 *  To the maximum extent permitted by applicable law, AMD 
 *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING 
 *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
 *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE 
 *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY 
 *  ACCOMPANYING WRITTEN MATERIALS.
 * 
 *  To the maximum extent permitted by applicable law, IN NO EVENT
 *  SHALL AMD BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING 
 *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS 
 *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
 *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.   
 * 
 *  AMD assumes no responsibility for the maintenance and support
 *  of this software.
 ********************************************************************/

/*

This file represents all the activities necessary to bring
the Au1200 out of reset. It sets all Au1200 resources to
known, usually disabled and safe, state.

This is an example startup file, tailored for the PbAu1200
reference board. PbAu1200-specific items are commented as
such, but in general are confined to the CPU endian
selection and memory controller values.

*/


/********************************************************************/

/*
 * MIPS ABI register defintions
 */
#define zero	$0
#define v0		$2
#define v1		$3
#define a0		$4
#define a1		$5
#define a2		$6
#define a3		$7
#define t0		$8
#define t1		$9
#define t2		$10
#define t3		$11
#define t4		$12
#define t5		$13
#define t6		$14
#define t7		$15
#define s0		$16
#define s1		$17
#define s2		$18
#define s3		$19
#define s4		$20
#define s5		$21
#define s6		$22
#define s7		$23
#define t8		$24
#define t9		$25
#define k0		$26
#define k1		$27
#define gp		$28
#define sp		$29
#define fp		$30
#define ra		$31

/********************************************************************/

/*
 * Au1200 CP0 registers
 */
#define CP0_Index		$0
#define CP0_Random		$1
#define CP0_EntryLo0	$2
#define CP0_EntryLo1	$3
#define CP0_Context		$4
#define CP0_PageMask	$5
#define CP0_Wired		$6
#define CP0_BadVAddr	$8
#define CP0_Count		$9
#define CP0_EntryHi		$10
#define CP0_Compare		$11
#define CP0_Status		$12
#define CP0_Cause		$13
#define CP0_EPC			$14
#define CP0_PRId		$15
#define CP0_Config		$16
#define CP0_Config0		$16
#define CP0_Config1		$16,1
#define CP0_LLAddr		$17
#define CP0_WatchLo		$18
#define CP0_IWatchLo	$18,1
#define CP0_WatchHi		$19
#define CP0_IWatchHi	$19,1
#define CP0_Scratch		$22
#define CP0_Debug		$23
#define CP0_DEPC		$24
#define CP0_PerfCnt		$25
#define CP0_PerfCtrl	$25,1
#define CP0_DTag		$28
#define CP0_DData		$28,1
#define CP0_ITag		$29
#define CP0_IData		$29,1
#define CP0_ErrorEPC	$30
#define CP0_DESave		$31

/********************************************************************/

/*
 * Au1200 base addresses (in KSEG1 region)
 */
#define AU1200_MEM_ADDR		0xB4000000
#define AU1200_MAEBE_ADDR	0xB4010000
#define AU1200_MAEFE_ADDR	0xB4012000
#define AU1200_DDMA_ADDR    0xB4003000
#define AU1200_MSR_ADDR		0xB4020000
#define AU1200_OTG_ADDR		0xB4020020
#define AU1200_OHC_ADDR		0xB4020100
#define AU1200_EHC_ADDR		0xB4020200
#define AU1200_DEV_ADDR		0xB4022000
#define AU1200_CIM_ADDR		0xB4004000
#define AU1200_LCD_ADDR		0xB5000000
#define AU1200_IC0_ADDR     0xB0400000
#define AU1200_UART0_ADDR   0xB1100000
#define AU1200_UART1_ADDR   0xB1200000
#define AU1200_SWC_ADDR		0xB1100100
#define AU1200_GPIO2_ADDR	0xB1700000
#define AU1200_IC1_ADDR     0xB1800000
#define AU1200_SYS_ADDR		0xB1900000
#define AU1200_PSC0_ADDR    0xB1A00000
#define AU1200_PSC1_ADDR	0xB1B00000
#define AU1200_AES_ADDR		0xB0300000	// fix!!! cant be right
#define AU1200_SD0_ADDR		0xB0600000
#define AU1200_SD1_ADDR		0xB0680000


/*
 * Au1200 memory controller register offsets
 */
#define mem_sdmode0	    	0x0800
#define mem_sdmode1	    	0x0808
#define mem_sdaddr0    		0x0820
#define mem_sdaddr1    		0x0828
#define mem_sdconfiga		0x0840
#define mem_sdconfigb		0x0848
#define mem_sdstat		    0x0850
#define mem_sdwrmd0 		0x0880
#define mem_sdwrmd1 		0x0888
#define mem_sdprecmd  	    0x08C0
#define mem_sdautoref 	    0x08C8
#define mem_sdsref  	    0x08D0

#define mem_stcfg0		    0x1000
#define mem_sttime0		    0x1004
#define mem_staddr0		    0x1008
#define mem_stcfg1		    0x1010
#define mem_sttime1		    0x1014
#define mem_staddr1		    0x1018
#define mem_stcfg2		    0x1020
#define mem_sttime2		    0x1024
#define mem_staddr2		    0x1028
#define mem_stcfg3		    0x1030
#define mem_sttime3		    0x1034
#define mem_staddr3		    0x1038
#define mem_staltime		0x1040
#define mem_stndctrl		0x1100


/*
 * Au1200 peripheral register offsets
 */
#define ddma_inten			0x000C
#define psc_enable		    0x0004		
#define uart_enable		    0x0100
#if 0
#define maebe_ctlenable		0x0700
#define cim_enable			0x0000
#define lcd_screen			0x0004
#define swc_control			0x0000
#endif

#define ic_cfg0clr		    0x0044
#define ic_cfg1clr		    0x004C
#define ic_cfg2clr		    0x0054
#define ic_srcset		    0x0058
#define ic_assignset	    0x0060
#define ic_wakeclr		    0x006C
#define ic_maskclr		    0x0074
#define ic_risingclr	    0x0078
#define ic_fallingclr	    0x007C
#define ic_testbit		    0x0080

#define sys_scratch0	    0x0018
#define sys_scratch1	    0x001c
#define sys_cntctrl		    0x0014
#define sys_freqctrl0	    0x0020
#define sys_freqctrl1	    0x0024
#define sys_clksrc		    0x0028
#define sys_pinfunc		    0x002C
#define sys_wakemsk		    0x0034
#define sys_powerctrl	    0x003C
#define sys_endian		    0x0038
#define sys_wakesrc		    0x005C
#define sys_cpupll		    0x0060
#define sys_auxpll		    0x0064
#define sys_trioutclr	    0x0100
#define sys_outputset		0x0108
#define sys_outputclr	    0x010C
#define sys_pininputen	    0x0110

#define gpio2_dir		    0x0000
#define gpio2_output	    0x0008
#define gpio2_pinstate	    0x000C
#define gpio2_inten		    0x0010
#define gpio2_enable	    0x0014

/********************************************************************/

/*
 * PbAu1200-specific values
 * NOTE: All values are for operation at 396MHz, SD=2
 */

#define SYS_CPUPLL		33	/* 396Mhz */
#define SYS_POWERCTRL	0	/* SD=2   */
#define SYS_AUXPLL		8	/* 96MHz for LCD */

/*
 * With SBUS of 198MHz and mem_stcfg0[TS]=0, static bus controller
 * clock period is 5ns
 */

/* Address Latch Timing - SN74LVC16374ADVG latch on rising edge of ALE
  Tah=000 (0   clocks)
  Tlw=000 (1+0 clocks)
 Tasu=001 (1   clocks) Latch needs 3ns
 */
#define MEM_STALTIME 0x00000001

/* RCE0: 128MB Spansion S29GL512N10T MirrorBit Flash - 100ns, Vio=3V
         Data sheet S29GLxxxN_MirrorBit.pdf data May 13, 2004

 Tcsoe= (1+0  clocks) data sheet specs MAX(tCE 110ns - tOE 25ns), choose 5ns for stable address, AS=1
 Toecs= (0+0  clocks) data sheet specs   0ns, AH=0
  Twcs= (1+0  clocks) data sheet specs   0ns for tCH
  Tcsh= (1+6  clocks) data sheet specs MAX(tWPH 30ns, tCEH 35ns)
Tcsoff= (1+6  clocks) match Tcsh
   Twp= (1+6  clocks) data sheet specs  35ns for tWP
  Tcsw= (1+0  clocks) data sheet specs   0ns for tCS
   Tpm= (1+4  clocks) data sheet specs  25ns for tPACC
    Ta= (1+19 clocks) data sheet specs 100ns for tRC

mem_stcfg0: 0000 0000 0010 1101 0001 0000 0100 0011 : 0x002D1043
Tcsoe=000 (see above)
Toecs=000 (see above)
   AH=0   (not needed)
   NW=0   (n/a)
   AS=1   (setup needed)
    S=0   (asynchronous)
   DE=1   (de-assert)
 MBSa=1
  MBC=0
   TA=1   (Tcsh for reads and writes)
  DIV=000 (n/a)
  ALD=0   (address latch enable)
   AV=0   (no address visibility)
   BE=0   (little endian)
   TS=0   (asynchronous operation)
   EW=0   (n/a)
 MBSb=1
   BS=0   (n/a)
   PM=0   (disable page mode)
   RO=0   (writable)
  DTY=3   (NOR Flash)

mem_sttime0: 0000 0110 0110 0001 1000 0001 0001 0011 : 0x06618113
  Twcs=000