aab.vhd

假前做了电子课程设计,感触颇深。老师安排一个题目,在一周时间里拿出成果。我们从熟悉quartus软件,到自学vhdl语言,再到设计程序,

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity aab is
  port(d:in std_logic_vector(2 downto 0);
       clk,hang,lie,i,o:in std_logic;
       q:out std_logic_vector(7 downto 0);
       sel:in std_logic_vector(2 downto 0));
end aab;
architecture aaa_arc of aab is
type park is array (0 to 7)of std_logic_vector(7 downto 0);
begin
  process(clk)
  variable tmp:park;
  variable l,h:std_logic_vector(2 downto 0);
  variable ll,hh:integer range 0 to 7;
  variable x:std_logic;
  begin
    if clk'event and clk='1'then
      if x='0'then
        tmp(0):="11111111";
        tmp(1):="11111111";
        tmp(2):="11111111";
        tmp(3):="11111111";
        tmp(4):="11111111";
        tmp(5):="11111111";
        tmp(6):="11111111";
        tmp(7):="11111111";
        x:='1';
      else
        if hang='0'then
           h:=d;
           hh:=conv_integer(h);
        elsif lie='0'then
           l:=d;
           ll:=conv_integer(l);
        elsif i='0'then
           tmp(ll)(hh):='0';
        elsif o='0'then
           tmp(ll)(hh):='1';
        end if;
        case sel is
           when "000"=>q<=tmp(0);
           when "001"=>q<=tmp(1);
           when "010"=>q<=tmp(2);
           when "011"=>q<=tmp(3);
           when "100"=>q<=tmp(4);
           when "101"=>q<=tmp(5);
           when "110"=>q<=tmp(6);
           when "111"=>q<=tmp(7);
           when others=>null;
        end case;
      end if;
    end if;
  end process;
end aaa_arc;


library ieee;
use ieee.std_logic_1164.all;
entity sss is
  port(clk:in std_logic;
       a:in std_logic_vector(2 downto 0);
       q:out std_logic_vector(2 downto 0));
end sss;
architecture sss_arc of sss is
begin
  process(clk)
  begin
    if clk'event and clk='1'then
      q<=a;
    end if;
  end process;
end sss_arc;



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sel is
  port(clk:in std_logic;
       q:out std_logic_vector(2 downto 0));    
end sel;
architecture sel_arc of sel is
begin 
  process(clk)
  variable cnt:std_logic_vector(2 downto 0);
  begin 
    if clk'event and clk='1'then
      cnt:=cnt+1;
    end if;
    q<=cnt;
  end process;
end sel_arc;