rominit.s

powerpc 系列cpu mpc860ads vxworks BSP 得花钱买的

        lis     r11, HIADJ ((REFRESH_VALUE / 2) << MAMR_PTA_SHIFT)
        addi    r11, r11, LO ((REFRESH_VALUE / 2) << MAMR_PTA_SHIFT)

mptprInit:
	/* program the MPTPR */

	sth	r6, MPTPR(0)(r4)
 
        /* 
	 * initialize MxMR but don't enable refresh until after 
	 * SDRAM initialization.
         */

        lis     r6, HIADJ (MAMR_DEFAULT_VALUE)
        addi    r6, r6, LO (MAMR_DEFAULT_VALUE)
        or      r6, r6, r11                      
        stw     r6, MAMR(0)(r4)

        lis     r6, HIADJ (MBMR_DEFAULT_VALUE)
        addi    r6, r6, LO (MBMR_DEFAULT_VALUE)
        or      r6, r6, r11                     
        stw     r6, MBMR(0)(r4)

#ifndef INCLUDE_SDRAM

	/* get the DRAM speed */

	lis	r5, HIADJ(BCSR2)	/* load r5 with the BCSR2 address */
	lwz	r6, LO(BCSR2)(r5)	/* load r6 with the BCSR2 value */
	lis     r5, HI(BCSR2_DRAM_PD_SPEED_MASK)
	and	r6, r6, r5

	lis     r5, HI(BCSR2_DRAM_PD_60NS_SIMM)
	cmpw	r6, r5
	beq	dram60ns

	lis     r5, HI(BCSR2_DRAM_PD_70NS_SIMM)
	cmpw	r6, r5
	beq	dram70ns

dram60ns:
#ifndef	EDO_DRAM
	/*
	 * load r6/r7 with the start/end address of the UPM table for a
	 * none EDO 60ns Dram.
	 */

	lis	r6, HIADJ( UpmTable60)
	addi	r6, r6, LO(UpmTable60)

	lis	r7, HIADJ( UpmTable60End)
	addi	r7, r7, LO(UpmTable60End)
	b	upmaInit	
#endif

dramEdo60ns:
	/*
	 * load r6/r7 with the start/end address of the UPM table for an
	 * EDO 60ns Dram.
	 */

	lis	r6, HIADJ( UpmTableEdo60)
	addi	r6, r6, LO(UpmTableEdo60)

	lis	r7, HIADJ( UpmTableEdo60End)
	addi	r7, r7, LO(UpmTableEdo60End)
	b	upmaInit	

dram70ns:
#ifndef	EDO_DRAM
	/*
	 * load r6/r7 with the start/end address of the UPM table for a
	 * none EDO 70ns Dram.
	 */

	lis	r6, HIADJ( UpmTable70)
	addi	r6, r6, LO(UpmTable70)

	lis	r7, HIADJ( UpmTable70End)
	addi	r7, r7, LO(UpmTable70End)
	b	upmaInit	
#endif

dramEdo70ns:
	/*
	 * load r6/r7 with the start/end address of the UPM table for an
	 * EDO 70ns Dram.
	 */

	lis	r6, HIADJ( UpmTableEdo70)
	addi	r6, r6, LO(UpmTableEdo70)

	lis	r7, HIADJ( UpmTableEdo70End)
	addi	r7, r7, LO(UpmTableEdo70End)
	b	upmaInit	

upmaInit:
	/* init UPMA for memory access */

	sub	r5, r7, r6		/* compute table size */
	srawi	r5, r5, 2		/* in integer size */

	/* convert UpmTable to ROM based addressing */

	lis	r7, HIADJ(romInit)	
	addi	r7, r7, LO(romInit)

	lis	r8, HIADJ(ROM_TEXT_ADRS)
	addi	r8, r8, LO(ROM_TEXT_ADRS)

	sub	r6, r6, r7		/* subtract romInit base address */
	add	r6, r6, r8 		/* add in ROM_TEXT_ADRS address */

					/* Command: OP=Write, UPMA, MAD=0 */
	lis	r9, HIADJ (MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS0)
	addi	r9, r9, LO(MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS0)

UpmaWriteLoop:	
	/* write the UPM table in the UPM */

	lwz	r10, 0(r6)		/* get data from table */
	stw	r10, MDR(0)(r4)		/* store the data to MD register */

	stw	r9, MCR(0)(r4)		/* issue command to MCR register */

	addi	r6, r6, 4		/* next entry in the table */
	addi	r9, r9, 1		/* next MAD address */
	cmpw	r9, r5			/* done yet ? */
	blt	UpmaWriteLoop

	/* get the DRAM size, and Map the bank 2 & 3 to the Dram area */

	lis	r5, HIADJ(BCSR2)	/* load r5 with the BCSR2 address */
	lwz	r6, LO(BCSR2)(r5)	/* load r6 with the BCSR2 value */
	lis	r5, HI(BCSR2_DRAM_PD_SIZE_MASK)
	and	r6, r6, r5

	lis	r5, HI(BCSR2_DRAM_PD_4MEG_SIMM)
	cmpw	r6, r5
	beq	dram4meg

	lis	r5, HI(BCSR2_DRAM_PD_8MEG_SIMM)
	cmpw	r6, r5
	beq	dram8meg

	lis	r5, HI(BCSR2_DRAM_PD_16MEG_SIMM)
	cmpw	r6, r5
	beq	dram16meg

	lis	r5, HI(BCSR2_DRAM_PD_32MEG_SIMM)
	cmpw	r6, r5
	beq	dram32meg

dram32meg:
	/* program BR3 */

	lis	r5, HIADJ( ((0x01000000 + LOCAL_MEM_LOCAL_ADRS) & \
				BR_BA_MSK) | BR_MS_UPMA | BR_V)
	addi	r5, r5, LO(((0x01000000 + LOCAL_MEM_LOCAL_ADRS) & \
				BR_BA_MSK) | BR_MS_UPMA | BR_V)
	stw	r5, BR3(0)(r4)

dram16meg:	
	/* compute the OR3/OR2 value for a 16M block size */

	lis	r5, HIADJ(0xff000000 | OR_CSNT_SAM)
	addi	r5, r5, LO(0xff000000 | OR_CSNT_SAM)
	stw	r5, OR3(0)(r4)	/* Set OR3. Used only when BR3 is valid */

        /* change the Address Multiplexing in MAMR */
 
        lwz     r6, MAMR(0)(r4)
        lis     r9, HIADJ(~MAMR_AMA_MSK)
        addi    r9, r9, LO(~MAMR_AMA_MSK)
        and     r6, r6, r9              /* clear the AMA bits in MAMR */
        lis     r9, HIADJ(MAMR_AMA_TYPE_3)
        addi    r9, r9, LO(MAMR_AMA_TYPE_3)
        or      r6, r6, r9              /* set the AMA bits */
        stw     r6, MAMR(0)(r4)
 
        b       dramInit

dram8meg:
	/* program BR3 */

	lis	r5, HIADJ( ((0x00400000 + LOCAL_MEM_LOCAL_ADRS) & \
				BR_BA_MSK) | BR_MS_UPMA | BR_V)
	addi	r5, r5, LO(((0x00400000 + LOCAL_MEM_LOCAL_ADRS) & \
				BR_BA_MSK) | BR_MS_UPMA | BR_V)
	stw	r5, BR3(0)(r4)

dram4meg:	
	/* compute the OR3/OR2 value for a 4M block size */

	lis	r5, HIADJ( 0xffc00000 | OR_CSNT_SAM)
	addi	r5, r5, LO(0xffc00000 | OR_CSNT_SAM)
	stw	r5, OR3(0)(r4)	/* Set OR3. Used only when BR3 is valid */
	b	dramInit

		
dramInit:	
	/* Map the bank 2 to the Dram area */

	stw	r5, OR2(0)(r4)	/* set OR2 to the previously computed value */

	lis	r5, HIADJ( (LOCAL_MEM_LOCAL_ADRS & BR_BA_MSK) | BR_MS_UPMA | \
			    BR_V)
	addi	r5, r5, LO((LOCAL_MEM_LOCAL_ADRS & BR_BA_MSK) | BR_MS_UPMA | \
			    BR_V)
	stw	r5, BR2(0)(r4)

#else /* INCLUDE_SDRAM */

upmbInit:
 
        /*
         * load r6/r7 with the start/end address of the UPM table for an
         * SDRAM @ 50MHZ.
         */

        lis     r6, HIADJ( upmbTableSdram)
        addi    r6, r6, LO(upmbTableSdram)
        lis     r7, HIADJ( upmbTableSdramEnd)
        addi    r7, r7, LO(upmbTableSdramEnd)
 
        /* init UPMB for memory access */
 
        sub     r5, r7, r6              /* compute table size */
        srawi   r5, r5, 2               /* in integer size */
 
        /* convert UpmTable to ROM based addressing */
 
        lis     r7, HIADJ(romInit)
        addi    r7, r7, LO(romInit)
 
        lis     r8, HIADJ(ROM_TEXT_ADRS)
        addi    r8, r8, LO(ROM_TEXT_ADRS)
 
        sub     r6, r6, r7              /* subtract romInit base address */
        add     r6, r6, r8              /* add in ROM_TEXT_ADRS address */
 
        lis     r9, HIADJ (MCR_OP_WRITE | MCR_UM_UPMB | MCR_MB_CS0)
        addi    r9, r9, LO(MCR_OP_WRITE | MCR_UM_UPMB | MCR_MB_CS0)
 
UpmbWriteLoop:
        /* write the UPM table in the UPM */
 
        lwz     r10, 0(r6)              /* get data from table */
        stw     r10, MDR(0)(r4)         /* store the data to MD register */
 
        stw     r9, MCR(0)(r4)          /* issue command to MCR register */
 
        addi    r6, r6, 4               /* next entry in the table */
        addi    r9, r9, 1               /* next MAD address */


        addi    r5,r5,-1
        cmpwi   r5,0
        bne     UpmbWriteLoop

        /* 
         * Issue precharge command (PRCG) and wait the precharge time (t-rp).
	 * Run precharge pattern from UPMB location 5.
         */

        lis     r5, HIADJ(MCR_OP_RUN | MCR_UM_UPMB | MCR_MB_CS4 | \
			  MCR_MCLF_1X | 0x5)
        addi    r5, r5, LO(MCR_OP_RUN | MCR_UM_UPMB | MCR_MB_CS4 | \
			   MCR_MCLF_1X | 0x5)
        stw     r5, MCR(0)(r4)
 
        /* run refresh pattern 8 times */

        lis     r5, HIADJ(MCR_OP_RUN | MCR_UM_UPMB | MCR_MB_CS4 | \
			  MCR_MCLF_8X | 0x30)
        addi    r5, r5, LO(MCR_OP_RUN | MCR_UM_UPMB | MCR_MB_CS4 | \
			  MCR_MCLF_8X | 0x30)
        stw     r5, MCR(0)(r4)
 
        /* 
	 * Configure the 32 bit address to be output on the address bus 
	 * if AMX = 0xb11.
         * See section 16.6.4.1 "Arm Words".  The following values must 
	 * be placed on the defined SDRAM address pins:
         *   A[9]   = 0          burst write mode
         *   A[6:4] = 010        cas latency of two
         *   A[3]   = 0          sequential mode
         *   A[2:0] = 010        burst length 4
         *
         * The address must be shifted left by 2 bits for 32 bit wide SDRAM...
         *   (0b0100010 << 2) = 0x88
         */

        lis     r5, HIADJ(LOCAL_MEM_LOCAL_ADRS | 0x88)
        addi    r5, r5, LO(LOCAL_MEM_LOCAL_ADRS | 0x88)
        stw     r5, MAR(0)(r4)
 
        /* 
	 * issue a mode register set (MRS) to initialize the SDRAM mode 
	 * register.  This programs the burst length, CAS latency and 
	 * write mode. Run MRS pattern from UPMB location 6.
         */

        lis     r5, HIADJ(MCR_OP_RUN | MCR_UM_UPMB | MCR_MB_CS4 | \
			  MCR_MCLF_1X | 0x6)
        addi    r5, r5, LO(MCR_OP_RUN | MCR_UM_UPMB | MCR_MB_CS4 | \
			  MCR_MCLF_1X | 0x6)
        stw     r5, MCR(0)(r4)

	/* program OR4 and BR4 for 4 Mbytes SDRAM Memory Array */

	lis	r5, HIADJ  ((~(SDRAM_SIZE - 1)) | OR_CSNT_SAM)
	addi    r5, r5, LO ((~(SDRAM_SIZE - 1)) | OR_CSNT_SAM)
	stw	r5, OR4(0)(r4)	/* set OR4 to the previously computed value */

	lis	r5, HIADJ ((LOCAL_MEM_LOCAL_ADRS & BR_BA_MSK) | BR_MS_UPMB \
			    | BR_V)
	addi    r5, r5, LO ((LOCAL_MEM_LOCAL_ADRS & BR_BA_MSK) | BR_MS_UPMB \
			    | BR_V)
	stw	r5, BR4(0)(r4)

	/* enable SDRAM refresh cycles */

        lis     r5, HIADJ (MBMR_DEFAULT_VALUE | MAMR_PTBE)
        addi    r5, r5,LO (MBMR_DEFAULT_VALUE | MAMR_PTBE)
	add	r5, r5, r11
        stw     r5, MBMR(0)(r4)

#endif /* INCLUDE_SDRAM */
 
	/* Get the board revision number */

	lis	r4, HIADJ(BCSR3)	/* load r4 with the BCSR3 address */
	lwz	r5, LO(BCSR3)(r4)	/* load r5 with the BCSR3 value */

	andis.	r6, r5, 0x3f00		/* 8xxFADS DRAM is active low */
	bgt	noEngBoard
	
	lis	r4, HI(BCSR3_BREVN)
	and	r5, r5, r4		/* extract board revision number */

        /* disable all devices (serial, ethernet, ...) */

	cmpwi	r5, 0			/* if board revision number is 0 */
	bne	noEngBoard 
	
	lis	r4, HI(BCSR1_RESET_VAL_ENG) /* then use the ENG reset val */
	bl	bscr1Init

noEngBoard:
	lis	r4, HI(BCSR1_RESET_VAL)		/* otherwise normal value */

#ifdef INCLUDE_SDRAM

	/* enable the SDRAM on the FADS8xx and disable the DRAM SIMM */

        lis     r5, HIADJ (BCSR1_SDRAM_EN | BCSR1_DRAM_EN)      
        or      r4, r4, r5                      /* or r5 with BCSR1 value */

#endif /* INCLUDE_SDRAM */

bscr1Init:
	lis	r5, HIADJ(BCSR1)
	stw	r4, LO(BCSR1)(r5)		/* reset the BCSR1 register */

#ifdef  FADS_860T
        lis     r4, HIADJ(BCSR4)                /* load r4 with BCSR4 address */
        lwz     r5, LO(BCSR4)(r4)               /* load r5 with BCSR4 value */
        lis     r4, HIADJ (BCSR4_UUFDIS)        /* load r4 with disable value */
        or      r5, r5, r4                      /* or r5 with new BCSR4 value */
        lis     r4, HIADJ (~BCSR4_FETH_RST)     /* load r4 with reset value */
        and     r5, r5, r4                      /* and r5 with BCSR4 value */
        lis     r4, HIADJ(BCSR4)                /* load r4 with BCSR4 address */
        stw     r5, LO(BCSR4)(r4)               /* reset the FEC tranceiver */
#endif
 
        /* initialize the stack pointer */
	lis	sp, HIADJ(STACK_ADRS)
	addi	sp, sp, LO(STACK_ADRS)