rominit.s

powerpc 系列cpu mpc860ads vxworks BSP 得花钱买的

/* romInit.s - Motorola 860ads ROM initialization module */

/* Copyright 1984-1996 Wind River Systems, Inc. */
	.data
	.globl  copyright_wind_river
	.long   copyright_wind_river

/*
modification history
--------------------
01q,10may02,dtr  Adding code for SPR34619. MPC860 Errata SIU9.
01p,30oct01,dtr  Matching new coding convention.
01o,23oct01,dtr  Fix for SPR 65678. Boot lockup problem. USE_KEYED_REGS.
01n,08may01,pch  Add assembler abstractions (FUNC_EXPORT, FUNC_BEGIN, etc.)
01m,26jan99,cn   added support for SDRAM (SPR# 24337). Also removed checks 
		 to BCSR2_DRAM_NO_EDO_L and BCSR2_DRAM_EDO_L as this bit 
		 is not actually implemented.  
01l,09nov98,cn   added support for FADS860T boards.
01k,30jul98,gls  fixed to initialize CS0/CS1 earlier to allow access to BCSR3
01j,18feb98,gls	 added support for PPC823FADS
01i,23jun97,map  fixed MAMR init for 16/32 DRAM [SPR# 8753]
01h,17dec96,tpr  fixed MAMR init. bug with 16 and 32 Mbytes dram (SPR #7661)
01g,10nov96,tpr  updated UPM table. 
		 removed RTCSC initialization.
01f,08nov96,tpr  modified UPM table for EDO Dram @ 50 Mhz.
01e,06nov96,tpr  replaced PLPRCR_MF_SFT by PLPRCR_MF_SHIFT.
01d,06nov96,tpr  Clean up the code (SPR #7336).
		 added DRAM speed selection (SPR #7335).
01c,24jun96,tpr  Reworked all initialization code.
01b,04jun96,cah  Add mem controller minimal init sequence
01a,19apr96,tpr  written.
*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "regs.h"	
#include "sysLib.h"
#include "drv/multi/ppc860Siu.h"
	
#define MAMR_DEFAULT_VALUE (MAMR_PTAE | MAMR_AMA_TYPE_2 | 		\
			    MAMR_DSA_1_CYCL | MAMR_G0CLA_A12 | 		\
			    MAMR_GPL_A4DIS | MAMR_RLFA_1X | 		\
			    MAMR_WLFA_1X | MAMR_TLFA_4X)
 
#define MBMR_DEFAULT_VALUE (MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | 	\
			    MAMR_G0CLA_A11 | MAMR_RLFA_1X | 		\
			    MAMR_WLFA_1X | MAMR_TLFA_1X)

	/* internals */

	FUNC_EXPORT(_romInit)		/* start of system code */
	FUNC_EXPORT(romInit)		/* start of system code */
	
	/* externals */

	.extern romStart	/* system initialization routine */

	_WRS_TEXT_SEG_START

/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*

* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )

*/
FUNC_BEGIN(_romInit)
FUNC_BEGIN(romInit)
	bl	cold		/* jump to the cold boot initialization */
	
	bl	start		/* jump to the warm boot initialization */

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 1984-1996 Wind River Systems, Inc."
	.balign  _PPC_TEXT_SEG_ALIGN

cold:
	li	r3, BOOT_COLD	/* set cold boot as start type */

	/*
	 * When the PowerPC 860 is powered on, the processor fletch the
	 * instructions located at the address 0x100. We need to jump
	 * from the address 0x100 to the Flash space.
	 */

	lis	r4, HIADJ(start)		/* load r4 with the address */
	addi	r4, r4, LO(start)		/* of start */

	lis	r5, HIADJ(romInit)		/* load r5 with the address */
	addi	r5, r5, LO(romInit)		/* of romInit() */

	lis	r6, HIADJ(ROM_TEXT_ADRS)	/* load r6 with the address */
	addi	r6, r6, LO(ROM_TEXT_ADRS)	/* of ROM_TEXT_ADRS */

	sub	r4, r4, r5			/*  */
	add	r4, r4, r6 

	mtspr	LR, r4				/* save destination address*/
						/* into LR register */
	blr					/* jump to flash mem address */
			
start:
	/* set the MSR register to a known state */

	xor	r4, r4, r4		/* clear register R4 */
	mtmsr 	r4			/* cleat the MSR register */

	/* DER - clear the Debug Enable Register */

	mtspr	DER, r4

	/* ICR - clear the Interrupt Cause Register */

	mtspr	ICR, r4

	/* 
	 * ICTRL - initialize the Intstruction Support Control register
	 *	   
	 */

	lis	r5, HIADJ(0x00000007)
	addi	r5, r5, LO(0x00000007)
	mtspr	ICTRL, r5

	/* disable the instruction/data cache */
	
	lis	r4, HIADJ ( CACHE_CMD_DISABLE)		/* load disable cmd */
	addi	r4, r4, LO (CACHE_CMD_DISABLE)
	mtspr	IC_CST, r4				/* disable I cache */
	mtspr	DC_CST, r4				/* disable D cache */

	/* unlock the instruction/data cache */

	lis	r4, HIADJ ( CACHE_CMD_UNLOCK_ALL)	/* load unlock cmd */
	addi	r4, r4, LO (CACHE_CMD_UNLOCK_ALL)
	mtspr	IC_CST, r4			/* unlock all I cache lines */
	mtspr	DC_CST, r4			/* unlock all D cache lines */

	/* invalidate the instruction/data cache */

	lis	r4, HIADJ (CACHE_CMD_INVALIDATE)   /* load invalidate cmd*/
	addi	r4, r4, LO (CACHE_CMD_INVALIDATE)
	mtspr	IC_CST, r4		/* invalidate all I cache lines */
	mtspr	DC_CST, r4		/* invalidate all D cache lines */

	/*
	 * initialize the IMMR register before any non-core registers
	 * modification.
	 */

	lis	r4, HIADJ( INTERNAL_MEM_MAP_ADDR)	
	addi	r4, r4, LO(INTERNAL_MEM_MAP_ADDR)
	mtspr	IMMR, r4		/* initialize the IMMR register */

	mfspr	r4, IMMR		/* read it back, to be sure */
	rlwinm  r4, r4, 0, 0, 15	/* only high 16 bits count */

	/* SYPCR - turn off the system protection stuff */
	
	lis	r5, HIADJ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
	addi	r5, r5, LO(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
	stw	r5, SYPCR(0)(r4)

	/*
	 * Map the bank 0 to the flash area - On the ADS board at reset time
	 * the bank 0 is already used to map the flash.
	 */

	lis	r5, HIADJ( (ROM_BASE_ADRS & BR_BA_MSK) | BR_V)
	addi	r5, r5, LO((ROM_BASE_ADRS & BR_BA_MSK) | BR_V)
	stw	r5, BR0(0)(r4)


	lis	r5, HIADJ( 0xffe00000 | OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | \
			   OR_TRLX)
	addi	r5, r5, LO(0xffe00000 | OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | \
			   OR_TRLX)
	stw	r5, OR0(0)(r4)
	
	/*
	 * Map the bank 1 to the Board Status and Control Registers
	 */

	lis	r5, HIADJ( (BCSR0 & BR_BA_MSK) | BR_V)
	addi	r5, r5, LO((BCSR0 & BR_BA_MSK) | BR_V)
	stw	r5, BR1(0)(r4)

	lis	r5, HIADJ( (0xffff8000 & OR_AM_MSK) | OR_BI | OR_SCY_1_CLK)
	addi	r5, r5, LO((0xffff8000 & OR_AM_MSK) | OR_BI | OR_SCY_1_CLK)
	stw	r5, OR1(0)(r4)
	
	
	/* Check for FADS,  set the SIUMCR accordingly */
	
	lis	r5, HIADJ(BCSR3)	/* load r5 with the BCSR3 address */
	lwz	r6, LO(BCSR3)(r5)	/* load r6 with the BCSR3 value */
	
	andis.	r5, r6, 0x3f00		/* Check for FADS board */
	bgt	fads

	/* set the SIUMCR register for important debug port, etc... stuff */

	lis	r6, HIADJ( SIUMCR_FRC	       | SIUMCR_DLK  | SIUMCR_DPC | \
			   SIUMCR_MLRC_3STATES | SIUMCR_AEME | SIUMCR_GB5E)
	addi	r6, r6, LO(SIUMCR_FRC	       | SIUMCR_DLK  | SIUMCR_DPC | \
			   SIUMCR_MLRC_3STATES | SIUMCR_AEME | SIUMCR_GB5E)
	b	siu_done

fads:
	lis	r6, HIADJ(SIUMCR_DLK  | SIUMCR_DPC | \
			SIUMCR_MLRC_3STATES | SIUMCR_GB5E)
	addi	r6, r6, LO( SIUMCR_DLK  | SIUMCR_DPC | \
			SIUMCR_MLRC_3STATES | SIUMCR_GB5E)
	
siu_done:	

	lwz	r5, SIUMCR(0)(r4)
	or	r5, r5, r6
	stw	r5, SIUMCR(0)(r4)
        /* SPR 65678 - Lock the Key Registers (they protect the register
         * values from corruption on power cycle.  See MCG's EWT # 867 for
         * the symptoms and outcome of corrupted registers.
         *
         * r4 holds the address of the IMMR
         *
         * xxK registers are locked by writing any value other than 0x55CCAA33 
         * to the register, or by reading the register.  They are unlocked 
         * by writing 0x55CCAA33 to the register.  After locking, any write 
         * access to the locked SIU register will cause a MCE. (in one case,
         * not an MCE but a software emulation exception.  See the MPC860
         * user's manual, section 11 page 11 ff.)
         */
#ifdef USE_KEYED_REGS
        /* pre-loading r7 with '~KEYED_REG_UNLOCK_VALUE' (ie, 'lock it')
         * pre-loading r8 with ' KEYED_REG_UNLOCK_VALUE' (ie, 'unlock it')
         ***/
	lis    r7, HIADJ(  ~KEYED_REG_UNLOCK_VALUE ) 
	addi   r7, r7, LO( ~KEYED_REG_UNLOCK_VALUE )
	lis    r8, HIADJ(   KEYED_REG_UNLOCK_VALUE )
	addi   r8, r8, LO(  KEYED_REG_UNLOCK_VALUE )
#else
        /* pre-loading r7 with ' KEYED_REG_UNLOCK_VALUE' (ie, 'unlock it') */
	lis    r7, HIADJ(   KEYED_REG_UNLOCK_VALUE ) 
	addi   r7, r7, LO(  KEYED_REG_UNLOCK_VALUE )
#endif
	stw    r7, TBSCRK(0)(r4) 
	stw    r7, TBREFF0K(0)(r4)
	stw    r7, TBREFF1K(0)(r4)
	stw    r7, TBK(0)(r4)

	stw    r7, RTCSCK(0)(r4)
	stw    r7, RTCK(0)(r4)
	stw    r7, RTSECK(0)(r4)
	stw    r7, RTCALK(0)(r4)

	stw    r7, PISCRK(0)(r4)
	stw    r7, PITCK(0)(r4)
	stw    r7, SCCRK(0)(r4)
	stw    r7, PLPRCRK(0)(r4)

	stw    r7, RSRK(0)(r4)
        isync

	/* TBSCR - initialize the Time Base Status and Control register */
#ifdef USE_KEYED_REGS
	stw     r8, TBSCRK(0)(r4) /* others are TBREFF0K, TBREFF1K and TBK */
        isync
#endif
	lis	r5, HIADJ( TBSCR_REFA | TBSCR_REFB)
	addi	r5, r5, LO(TBSCR_REFA | TBSCR_REFB)
	sth	r5, TBSCR(0)(r4)
#ifdef USE_KEYED_REGS
	stw     r7, TBSCRK(0)(r4)
#endif
#ifdef USE_KEYED_REGS
	stw     r8, PISCRK(0)(r4) /* others are TBREFF0K, TBREFF1K and TBK */
        isync
#endif
	/* set PIT status and control init value */

	li	r5, PISCR_PS | PISCR_PITF
	sth	r5, PISCR(0)(r4)
#ifdef USE_KEYED_REGS
	stw     r7, PISCRK(0)(r4)
#endif
	/* set the SPLL frequency */

	lis	r5, HIADJ( (SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT) | \
								PLPRCR_TEXPS)
	addi	r5, r5, LO((SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT) | \
								PLPRCR_TEXPS)

#ifdef USE_KEYED_REGS
	stw     r8, PLPRCRK(0)(r4) /* others are TBREFF0K, TBREFF1K and TBK */
        isync
#endif

/*
* For Errata MPC860 SIU9 
* Delay to stop bus access while bus stablises after write to this register 
* Set delay to the longest bus access possible for your setup               
* Can cause reset if delay isn't long enough				     
* Note cache not enabled at this point
*/
	stw	r5, PLPRCR(0)(r4)
	isync
	divw	r5, r4, r4		/* waste time (r4 != 0) */
	divw	r5, r4, r5		/* 13 clocks		*/
	
#ifdef USE_KEYED_REGS
	stw     r7, PLPRCRK(0)(r4)
#endif
	/* 
	 * we program the MPTPR with the largest allowed divider 
	 * and the PTA value accordingly. So here we figure out the 
	 * correct value for the PTA field.
	 */

	li	r6, MPTPR_PTP_DIV64 
        lis     r11, HIADJ ((REFRESH_VALUE / 64) << MAMR_PTA_SHIFT)
        addi    r11, r11, LO ((REFRESH_VALUE / 64) << MAMR_PTA_SHIFT)
        cmpwi   r11,0
        bne     mptprInit

	/* try with the divider by 32 */

	li	r6, MPTPR_PTP_DIV32 
        lis     r11, HIADJ ((REFRESH_VALUE / 32) << MAMR_PTA_SHIFT)
        addi    r11, r11, LO ((REFRESH_VALUE / 32) << MAMR_PTA_SHIFT)
        cmpwi   r11,0
        bne     mptprInit

	/* try with the divider by 16 */

	li	r6, MPTPR_PTP_DIV16 
        lis     r11, HIADJ ((REFRESH_VALUE / 16) << MAMR_PTA_SHIFT)
        addi    r11, r11, LO ((REFRESH_VALUE / 16) << MAMR_PTA_SHIFT)
        cmpwi   r11,0
        bne     mptprInit

	/* try with the divider by 8 */

	li	r6, MPTPR_PTP_DIV8 
        lis     r11, HIADJ ((REFRESH_VALUE / 8) << MAMR_PTA_SHIFT)
        addi    r11, r11, LO ((REFRESH_VALUE / 8) << MAMR_PTA_SHIFT)
        cmpwi   r11,0
        bne     mptprInit

	/* try with the divider by 4 */

	li	r6, MPTPR_PTP_DIV4 
        lis     r11, HIADJ ((REFRESH_VALUE / 4) << MAMR_PTA_SHIFT)
        addi    r11, r11, LO ((REFRESH_VALUE / 4) << MAMR_PTA_SHIFT)
        cmpwi   r11,0
        bne     mptprInit

	/* it has to be the divide by 2 */

	li	r6, MPTPR_PTP_DIV2