pciop.h

Windows下Hardware直接读写

/*++

Copyright (c) 1997  Microsoft Corporation

Module Name:

    SIOCTL.H

Abstract:


    Defines the IOCTL codes that will be used by this driver.  The IOCTL code
    contains a command identifier, plus other information about the device,
    the type of access with which the file must have been opened,
    and the type of buffering.

Author:

    Eliyas Yakub - July 1997.

Environment:

    Kernel mode only.

Notes:

Revision History:

--*/
#pragma once

#ifdef _WINAPPS

typedef struct _PCI_SLOT_NUMBER {
  union {
    struct {
      ULONG  DeviceNumber:5;
      ULONG  FunctionNumber:3;
      ULONG  Reserved:24;
    } bits;
    ULONG  AsULONG;
  } u;
} PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;


#define PCI_TYPE0_ADDRESSES             6
#define PCI_TYPE1_ADDRESSES             2
#define PCI_TYPE2_ADDRESSES             5

typedef struct _PCI_COMMON_CONFIG {
    USHORT  VendorID;                   // (ro)
    USHORT  DeviceID;                   // (ro)
    USHORT  Command;                    // Device control
    USHORT  Status;
    UCHAR   RevisionID;                 // (ro)
    UCHAR   ProgIf;                     // (ro)
    UCHAR   SubClass;                   // (ro)
    UCHAR   BaseClass;                  // (ro)
    UCHAR   CacheLineSize;              // (ro+)
    UCHAR   LatencyTimer;               // (ro+)
    UCHAR   HeaderType;                 // (ro)
    UCHAR   BIST;                       // Built in self test

    union {
        struct _PCI_HEADER_TYPE_0 {
            ULONG   BaseAddresses[PCI_TYPE0_ADDRESSES];
            ULONG   CIS;
            USHORT  SubVendorID;
            USHORT  SubSystemID;
            ULONG   ROMBaseAddress;
            UCHAR   CapabilitiesPtr;
            UCHAR   Reserved1[3];
            ULONG   Reserved2;
            UCHAR   InterruptLine;      //
            UCHAR   InterruptPin;       // (ro)
            UCHAR   MinimumGrant;       // (ro)
            UCHAR   MaximumLatency;     // (ro)
        } type0;

// end_wdm end_ntminiport end_ntndis

        //
        // PCI to PCI Bridge
        //

        struct _PCI_HEADER_TYPE_1 {
            ULONG   BaseAddresses[PCI_TYPE1_ADDRESSES];
            UCHAR   PrimaryBus;
            UCHAR   SecondaryBus;
            UCHAR   SubordinateBus;
            UCHAR   SecondaryLatency;
            UCHAR   IOBase;
            UCHAR   IOLimit;
            USHORT  SecondaryStatus;
            USHORT  MemoryBase;
            USHORT  MemoryLimit;
            USHORT  PrefetchBase;
            USHORT  PrefetchLimit;
            ULONG   PrefetchBaseUpper32;
            ULONG   PrefetchLimitUpper32;
            USHORT  IOBaseUpper16;
            USHORT  IOLimitUpper16;
            UCHAR   CapabilitiesPtr;
            UCHAR   Reserved1[3];
            ULONG   ROMBaseAddress;
            UCHAR   InterruptLine;
            UCHAR   InterruptPin;
            USHORT  BridgeControl;
        } type1;

        //
        // PCI to CARDBUS Bridge
        //

        struct _PCI_HEADER_TYPE_2 {
            ULONG   SocketRegistersBaseAddress;
            UCHAR   CapabilitiesPtr;
            UCHAR   Reserved;
            USHORT  SecondaryStatus;
            UCHAR   PrimaryBus;
            UCHAR   SecondaryBus;
            UCHAR   SubordinateBus;
            UCHAR   SecondaryLatency;
            struct  {
                ULONG   Base;
                ULONG   Limit;
            }       Range[PCI_TYPE2_ADDRESSES-1];
            UCHAR   InterruptLine;
            UCHAR   InterruptPin;
            USHORT  BridgeControl;
        } type2;

// begin_wdm begin_ntminiport begin_ntndis

    } u;

    UCHAR   DeviceSpecific[192];

} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;


#endif


//
// Device type           -- in the "User Defined" range."
//
#define SIOCTL_TYPE 40000
//
// The IOCTL function codes from 0x800 to 0xFFF are for customer use.
//
#define IOCTL_PORT_READ_WRITE \
    CTL_CODE( SIOCTL_TYPE, 0x900, METHOD_BUFFERED, FILE_ANY_ACCESS  )

#define IOCTL_MEMORY_MAP \
    CTL_CODE( SIOCTL_TYPE, 0x901, METHOD_BUFFERED , FILE_ANY_ACCESS  )

#define IOCTL_MEMORY_READ_WRITE \
    CTL_CODE( SIOCTL_TYPE, 0x902, METHOD_OUT_DIRECT , FILE_ANY_ACCESS  )

#define IOCTL_SIOCTL_METHOD_BUFFERED \
    CTL_CODE( SIOCTL_TYPE, 0x903, METHOD_BUFFERED, FILE_ANY_ACCESS  )


#define IOCTL_SIOCTL_METHOD_NEITHER \
    CTL_CODE( SIOCTL_TYPE, 0x904, METHOD_NEITHER , FILE_ANY_ACCESS  )

#define IOCTL_PCIOP_ENUM_ALL \
	CTL_CODE( SIOCTL_TYPE, 0x801, METHOD_BUFFERED, FILE_ANY_ACCESS  )

#define IOCTL_PCIOP_GET_PCIDEVICE \
	CTL_CODE( SIOCTL_TYPE, 0x805, METHOD_BUFFERED, FILE_ANY_ACCESS  )


#define IOCTL_PCIOP_BUFFERED_TEST \
	CTL_CODE( SIOCTL_TYPE, 0x802, METHOD_BUFFERED, FILE_ANY_ACCESS  )

#define DRIVER_FUNC_INSTALL     0x01
#define DRIVER_FUNC_REMOVE      0x02

#define DRIVER_NAME       "Pciop"

//
//Pci query struct, input parameter
//
typedef struct PCIDevQuery{
	BOOLEAN first;
	ULONG vendorId;
	ULONG deviceId;
	ULONG busNum;
	PCI_SLOT_NUMBER slotNum;
}PCIDEVQUERY, *PPCIDEVQUERY;


//
//Pci query result struct, input parameter
//
typedef struct PCIQueryResult{
	PCIDEVQUERY pciQuery;
	PCI_COMMON_CONFIG pciComConfig;
}PCIQUERYRESULT, *PPCIQUERYRESULT;


//
//IO port read write request package
//the return is value read, or write result
//
typedef struct IOReadWritePack{
	BOOLEAN isRead;
	ULONG portAddress;
	ULONG portValue;
	ULONG rwSize;
}IOPORTRWP, *PIOPORTRWP;


//
//Memory read request package
//
typedef struct MemoryReadWritePack{
	BOOLEAN isRead;
	ULONG memoryAddress;
	ULONG rSize;
}MEMORYRP, *PMEMORYRP;