at91sam9260_sdram.mac

9260的ucos源码

// ---------------------------------------------------------
//   ATMEL Microcontroller Software Support  -  ROUSSET  -
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any  kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
//  File: SAM9_SDRAM.mac
//  User setup file for CSPY debugger.
//  1.1 08/Aug/06 jpp    : Creation
//
//  $Revision: 1.1 $
//
// ---------------------------------------------------------
__var __mac_i;
__var __mac_pt;

/*********************************************************************
*
*       execUserReset() : JTAG set initially to Full Speed
*/
execUserReset()
{
    __hw_reset(0);
    __message "------------------------------ execUserReset ---------------------------------";
    CheckNoRemap();
    ini();
    __PllSetting100MHz();
    __AIC();                                                    //* Init AIC
    __message "-------------------------------Set PC Reset ----------------------------------";
    __writeMemory32(0xD3,0x98,"Register");                      //*  Set CPSR
    __writeMemory32(0x20000000,0xB4,"Register");                //*  Set PC (R15)
}

/*********************************************************************
*
*       execUserPreload() : JTAG set initially to 32kHz
*/
execUserPreload()
{
    __message "------------------------------ execUserPreload ---------------------------------";
    __writeMemory32(0xD3,0x98,"Register");                      //*  Set CPSR
    __PllSetting();                                             //* Init PLL
    __PllSetting100MHz();
    __initSDRAM();                                              //* Init SDRAM before load
    __AIC();                                                    //* Init AIC
    CheckNoRemap();                                             //* Set the RAM memory at 0x0020 0000 & 0x0000 0000
    Watchdog();                                                 //* Watchdog Disable

                                                                //*  Get the Chip ID  (AT91C_DBGU_C1R & AT91C_DBGU_C2R
    __mac_i=__readMemory32(0xFFFFF240,"Memory");
    __message " ---------------------------------------- Chip ID   0x",__mac_i:%X;

    if ( __mac_i == 0x019803A1)  {__message " Chip ID for AT91SAM9260";}
    else { __message " Chip ID for unknown !!";}
    __mac_i=__readMemory32(0xFFFFF244,"Memory");
    __message " ---------------------------------------- Extention 0x",__mac_i:%X;
}

/*********************************************************************
*
*       __initSDRAM()
* Function description
* Set SDRAM for works at 100 MHz
**********************************************************************/

__initSDRAM()
{
    __writeMemory32(0x0001003A,0xFFFFEF1C,"Memory");            // pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC;

                                                                // Configure PIOs
    __writeMemory32(0xFFFF0000,0xFFFFF870,"Memory");            // pPio->PIO_ASR = periphAEnable; AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870)  // (PIOC) Select A Register
    __writeMemory32(0x00000000,0xFFFFF874,"Memory");            // pPio->PIO_BSR = periphBEnable;AT91C_PIOC_BSR  ((AT91_REG *) 0xFFFFF874)  // (PIOC) Select B Register
    __writeMemory32(0xFFFF0000,0xFFFFF804,"Memory");            // pPio->PIO_PDR = (periphAEnable | periphBEnable);                         // Set in Periph mode

    __writeMemory32(0x000002EE,0xFFFFEA04,"Memory");            // psdrc->SDRAMC_TR = 0x0008EF5A;

                                                                // psdrc->SDRAMC_CR =  AT91C_SDRAMC_NC_9  | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 |
                                                                // AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 |
                                                                // AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 ;
    __writeMemory32(0x85227279,0xFFFFEA08,"Memory");

    __sleep(100);

    __writeMemory32(0x00000002,0xFFFFEA00,"Memory");            //	psdrc->SDRAMC_MR    = 0x00000002;                       // Set PRCHG AL
    __writeMemory32(0x00000000,0x20000000,"Memory");            //	*AT91C_SDRAM	    = 0x00000000;                       // Perform PRCHG

    __sleep(100);

    __writeMemory32(0x00000004,0xFFFFEA00,"Memory");            //  psdrc->SDRAMC_MR    = AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 1st CBR
    __writeMemory32(0x00000001,0x20000010,"Memory");            // *(AT91C_SDRAM+4)     = 0x00000001;                       // Perform CBR
    __writeMemory32(0x00000004,0xFFFFEA00,"Memory");            //  psdrc->SDRAMC_MR    = 0x00000004;                       // Set 2 CBR
    __writeMemory32(0x00000002,0x20000020,"Memory");            // *(AT91C_SDRAM+8      = 0x00000002;                       // Perform CBR
    __writeMemory32(0x00000004,0xFFFFEA00,"Memory");            //  psdrc->SDRAMC_MR    = AT91C_SDRAMC_MODE_RFSH_CMD;       // Set 3 CBR
    __writeMemory32(0x00000003,0x20000030,"Memory");            // *(AT91C_SDRAM+0xc)   = 0x00000003;                       // Perform CBR
    __writeMemory32(0x00000004,0xFFFFEA00,"Memory");            //  psdrc->SDRAMC_MR    = AT91C_SDRAMC_MODE_RFSH_CMD;       // Set 4 CBR
    __writeMemory32(0x00000004,0x20000040,"Memory");            // *(AT91C_SDRAM+0x10)  = 0x00000004;                       // Perform CBR
    __writeMemory32(0x00000004,0xFFFFEA00,"Memory");            //	psdrc->SDRAMC_MR    = AT91C_SDRAMC_MODE_RFSH_CMD;       // Set 5 CBR
    __writeMemory32(0x00000005,0x20000050,"Memory");            //	*(AT91C_SDRAM+0x14) = 0x00000005;                       // Perform CBR
    __writeMemory32(0x00000004,0xFFFFEA00,"Memory");            //	psdrc->SDRAMC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;       // Set 6 CBR
    __writeMemory32(0x00000006,0x20000060,"Memory");            //	*(AT91C_SDRAM+0x18)	= 0x00000006;                       // Perform CBR
    __writeMemory32(0x00000004,0xFFFFEA00,"Memory");	        //	psdrc->SDRAMC_MR    = AT91C_SDRAMC_MODE_RFSH_CMD;       // Set 7 CBR
    __writeMemory32(0x00000007,0x20000070,"Memory");            //	*(AT91C_SDRAM+0x1c) = 0x00000007;                       // Perform CBR
    __writeMemory32(0x00000004,0xFFFFEA00,"Memory");            //	psdrc->SDRAMC_MR    = AT91C_SDRAMC_MODE_RFSH_CMD;       // Set 8 CBR
    __writeMemory32(0x00000008,0x20000080,"Memory");            //	*(AT91C_SDRAM+0x20) = 0x00000008;                       // Perform CBR
    __writeMemory32(0x00000003,0xFFFFEA00,"Memory");            //	psdrc->SDRAMC_MR    = AT91C_SDRAMC_MODE_LMR_CMD;        // Set LMR operation
    __writeMemory32(0xCAFEDEDE,0x20000090,"Memory");            //	*(AT91C_SDRAM+0x24) = 0xcafedede;                       // Perform LMR burst=1, lat=2
    __writeMemory32(0x000002B9,0xFFFFEA04,"Memory");            //	psdrc->SDRAMC_TR    = (AT91C_MASTER_CLOCK * 7)/1000000; // Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
    __writeMemory32(0x00000000,0xFFFFEA00,"Memory");            //	psdrc->SDRAMC_MR    = AT91C_SDRAMC_MODE_NORMAL_CMD;     // Set Normal mode
    __writeMemory32(0x00000000,0x20000000,"Memory");            //	*AT91C_SDRAM        = 0x00000000;                       // Perform Normal mode

    __message "------------------------------- SDRAM Done at 100 MHz -------------------------------";
}

/*********************************************************************
*
*       __PllSetting()
* Function description
*   Initializes the PMC.
*   1. Enable the Main Oscillator
*   2. Configure PLL
*   3. Switch Master
**********************************************************************/

__PllSetting()
{
     if ((__readMemory32(0xFFFFFC30,"Memory")&0x3) != 0 ) {
                                                                //* Disable all PMC interrupt ( $$ JPP)
                                                                //* AT91C_PMC_IDR   ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
        __writeMemory32(0xFFFFFFFF,0xFFFFFC64,"Memory");        //*    pPmc->PMC_IDR = 0xFFFFFFFF;
        __writeMemory32(0xFFFFFFFF,0xFFFFFC14,"Memory");        //* AT91C_PMC_PCDR  ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
        __writeMemory32(0xFFFFFFFE,0xFFFFFC04,"Memory");        // Disable all clock only Processor clock is enabled.
        __writeMemory32(0x00000001,0xFFFFFC30,"Memory");        // AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register

        __sleep(10000);

                                                                // write reset value to PLLA and PLLB
        __writeMemory32(0x00003F00,0xFFFFFC28,"Memory");        // AT91C_PMC_PLLAR ((AT91_REG *) 	0xFFFFFC28) // (PMC) PLL A Register
        __writeMemory32(0x00003F00,0xFFFFFC2C,"Memory");        // AT91C_PMC_PLLBR ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL B Register

        __sleep(10000);

        __emulatorSpeed(0);               //* Set JTAG speed to full speed

        __message "------------------------------- PLL  Enable -----------------------------------------";
    } else {
        __message " ********* Core in SLOW CLOCK mode ********* ";
    }
}

/*********************************************************************
*
*       __PllSetting100MHz()
* Function description
*   Set core at 200 MHz and MCK at 100 MHz
*********************************************************************/
__PllSetting100MHz()
{

    __message "------------------------------- PLL Set at 100 MHz ----------------------------------";