📄 7032_can.rpt
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25 26 B OUTPUT t 0 0 0 2 0 0 0 nIOR_P
23 27 B OUTPUT t 0 0 0 2 0 0 0 nIOW_p
19 31 B OUTPUT t 0 0 0 3 0 0 0 nMEMR_P
18 32 B OUTPUT t 0 0 0 3 0 0 0 nMEMW_P
27 24 B OUTPUT t 0 0 0 1 0 0 0 RST
6 8 A OUTPUT t 0 0 0 1 0 0 0 USBCON
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
Device-Specific Information: c:\max2work\bus\7032_can.rpt
7032_can
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+----- LC16 DIR1
| +--- LC15 nEXTBUS
| | +- LC8 USBCON
| | |
| | | Other LABs fed by signals
| | | that feed LAB 'A'
LC | | | | A B | Logic cells that feed LAB 'A':
Pin
37 -> - - - | - - | <-- ATABUSY
43 -> - * - | * - | <-- nGCS0
42 -> - * - | * * | <-- nGCS1
2 -> - * - | * - | <-- nGCS2
3 -> - * - | * * | <-- nGCS3
5 -> - * - | * - | <-- nGCS4
12 -> * - - | * * | <-- nOE
39 -> - - * | * * | <-- NRST
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\max2work\bus\7032_can.rpt
7032_can
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------- LC23 CANALE
| +--------------- LC18 CANCS0
| | +------------- LC17 CANRD
| | | +----------- LC22 CANWR
| | | | +--------- LC26 nIOR_P
| | | | | +------- LC27 nIOW_p
| | | | | | +----- LC31 nMEMR_P
| | | | | | | +--- LC32 nMEMW_P
| | | | | | | | +- LC24 RST
| | | | | | | | |
| | | | | | | | | Other LABs fed by signals
| | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | A B | Logic cells that feed LAB 'B':
Pin
44 -> - - - - * * * * - | - * | <-- ADDR24
37 -> - - - - - - - - - | - - | <-- ATABUSY
20 -> * * * * - - - - - | - * | <-- A0
21 -> * * * * - - - - - | - * | <-- A1
22 -> * * * * - - - - - | - * | <-- A2
42 -> * * * * - - - - - | * * | <-- nGCS1
3 -> - - - - - - * * - | * * | <-- nGCS3
12 -> - - * - * - * - - | * * | <-- nOE
39 -> - - - - - - - - * | * * | <-- NRST
13 -> * - - * - * - * - | - * | <-- nWE
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: c:\max2work\bus\7032_can.rpt
7032_can
** EQUATIONS **
ADDR24 : INPUT;
ATABUSY : INPUT;
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
A15 : INPUT;
A24 : INPUT;
D2 : INPUT;
D3 : INPUT;
EINT0 : INPUT;
nGCS0 : INPUT;
nGCS1 : INPUT;
nGCS2 : INPUT;
nGCS3 : INPUT;
nGCS4 : INPUT;
nOE : INPUT;
NRST : INPUT;
nWE : INPUT;
-- Node name is 'CANALE'
-- Equation name is 'CANALE', location is LC023, type is output.
CANALE = LCELL( _EQ001 $ GND);
_EQ001 = !A0 & !A1 & !A2 & !nGCS1 & !nWE;
-- Node name is 'CANCS0'
-- Equation name is 'CANCS0', location is LC018, type is output.
CANCS0 = LCELL( _EQ002 $ VCC);
_EQ002 = A0 & !A1 & !A2 & !nGCS1;
-- Node name is 'CANRD'
-- Equation name is 'CANRD', location is LC017, type is output.
CANRD = LCELL( _EQ003 $ VCC);
_EQ003 = A0 & !A1 & !A2 & !nGCS1 & !nOE;
-- Node name is 'CANWR'
-- Equation name is 'CANWR', location is LC022, type is output.
CANWR = LCELL( _EQ004 $ VCC);
_EQ004 = A0 & !A1 & !A2 & !nGCS1 & !nWE;
-- Node name is 'DIR1'
-- Equation name is 'DIR1', location is LC016, type is output.
DIR1 = LCELL( nOE $ GND);
-- Node name is 'nEXTBUS'
-- Equation name is 'nEXTBUS', location is LC015, type is output.
nEXTBUS = LCELL( _EQ005 $ GND);
_EQ005 = nGCS0 & nGCS1 & nGCS2 & nGCS3 & nGCS4;
-- Node name is 'nIOR_P'
-- Equation name is 'nIOR_P', location is LC026, type is output.
nIOR_P = LCELL( _EQ006 $ VCC);
_EQ006 = ADDR24 & !nOE;
-- Node name is 'nIOW_p'
-- Equation name is 'nIOW_p', location is LC027, type is output.
nIOW_p = LCELL( _EQ007 $ VCC);
_EQ007 = ADDR24 & !nWE;
-- Node name is 'nMEMR_P'
-- Equation name is 'nMEMR_P', location is LC031, type is output.
nMEMR_P = LCELL( _EQ008 $ VCC);
_EQ008 = !ADDR24 & !nGCS3 & !nOE;
-- Node name is 'nMEMW_P'
-- Equation name is 'nMEMW_P', location is LC032, type is output.
nMEMW_P = LCELL( _EQ009 $ VCC);
_EQ009 = !ADDR24 & !nGCS3 & !nWE;
-- Node name is 'RST'
-- Equation name is 'RST', location is LC024, type is output.
RST = LCELL(!NRST $ GND);
-- Node name is 'USBCON'
-- Equation name is 'USBCON', location is LC008, type is output.
USBCON = LCELL( NRST $ GND);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information c:\max2work\bus\7032_can.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000AE' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,364K
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