📄 7032_can.rpt
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Project Information c:\max2work\bus\7032_can.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 06/10/2005 16:49:51
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
7032_can EPM7032AETC44-10 18 12 0 12 0 37 %
User Pins: 18 12 0
Project Information c:\max2work\bus\7032_can.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Ignored primitive symbol "AND8" (ID :10) it has no output
Warning: Project has user pin or logic cell assignments, but has never been compiled before. For best fitting results, let the Compiler choose the first set of assignments instead.
Info: Reserved unused input pin 'A24' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'D3' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'D2' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'ATABUSY' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'EINT0' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Info: Reserved unused input pin 'A15' for future use because it has a pin assignment -- pin is tri-stated and must be connected to your board
Warning: Node 'nGCS5' has assignments but doesn't exist or is a primitive array -- edit the project's ACF to fix the problem
Project Information c:\max2work\bus\7032_can.rpt
** PIN/LOCATION/CHIP ASSIGNMENTS **
Actual
User Assignments
Assignments (if different) Node Name
7032_can@44 ADDR24
7032_can@37 ATABUSY
7032_can@20 A0
7032_can@21 A1
7032_can@22 A2
7032_can@10 A15
7032_can@8 A24
7032_can@28 CANALE
7032_can@34 CANCS0
7032_can@35 CANRD
7032_can@30 CANWR
7032_can@15 DIR1
7032_can@31 D2
7032_can@33 D3
7032_can@11 EINT0
7032_can@14 nEXTBUS
7032_can@43 nGCS0
7032_can@42 nGCS1
7032_can@2 nGCS2
7032_can@3 nGCS3
7032_can@5 nGCS4
7032_can@44 --------- nGCS5
7032_can@25 nIOR_P
7032_can@23 nIOW_p
7032_can@19 nMEMR_P
7032_can@18 nMEMW_P
7032_can@12 nOE
7032_can@39 NRST
7032_can@13 nWE
7032_can@27 RST
7032_can@6 USBCON
Project Information c:\max2work\bus\7032_can.rpt
** FILE HIERARCHY **
|74154:86|
Device-Specific Information: c:\max2work\bus\7032_can.rpt
7032_can
***** Logic for device '7032_can' compiled without errors.
Device: EPM7032AETC44-10
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffffffff
MultiVolt I/O = OFF
Device-Specific Information: c:\max2work\bus\7032_can.rpt
7032_can
** ERROR SUMMARY **
Info: Chip '7032_can' in device 'EPM7032AETC44-10' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
A
A V T C
D n n C A C A
D G G C N B A N
R C C I G R G U G N C
2 S S N N S N S N R S
4 0 1 T D T D Y D D 0
-----------------------------------_
/ 44 43 42 41 40 39 38 37 36 35 34 |
#TDI | 1 33 | D3
nGCS2 | 2 32 | #TDO
nGCS3 | 3 31 | D2
GND | 4 30 | CANWR
nGCS4 | 5 29 | VCCIO
USBCON | 6 EPM7032AETC44-10 28 | CANALE
#TMS | 7 27 | RST
A24 | 8 26 | #TCK
VCCIO | 9 25 | nIOR_P
A15 | 10 24 | GND
EINT0 | 11 23 | nIOW_p
|_ 12 13 14 15 16 17 18 19 20 21 22 _|
------------------------------------
n n n D G V n n A A A
O W E I N C M M 0 1 2
E E X R D C E E
T 1 I M M
B N W R
U T _ _
S P P
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GND* = These I/O pins can either be left unconnected or connected to GND. Connecting these pins to GND will improve the device's immunity to noise.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: c:\max2work\bus\7032_can.rpt
7032_can
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 3/16( 18%) 16/16(100%) 0/16( 0%) 7/36( 19%)
B: LC17 - LC32 9/16( 56%) 16/16(100%) 0/16( 0%) 9/36( 25%)
Total dedicated input pins used: 2/4 ( 50%)
Total I/O pins used: 32/32 (100%)
Total logic cells used: 12/32 ( 37%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 12/32 ( 37%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 3.08
Total fan-in: 37
Total input pins required: 18
Total fast input logic cells required: 0
Total output pins required: 12
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 12
Total flipflops required: 0
Total product terms required: 12
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: c:\max2work\bus\7032_can.rpt
7032_can
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
44 (3) (A) INPUT 0 0 0 0 0 4 0 ADDR24
37 - - INPUT 0 0 0 0 0 0 0 ATABUSY
20 (30) (B) INPUT 0 0 0 0 0 4 0 A0
21 (29) (B) INPUT 0 0 0 0 0 4 0 A1
22 (28) (B) INPUT 0 0 0 0 0 4 0 A2
10 (11) (A) INPUT 0 0 0 0 0 0 0 A15
8 (10) (A) INPUT 0 0 0 0 0 0 0 A24
31 (21) (B) INPUT 0 0 0 0 0 0 0 D2
33 (19) (B) INPUT 0 0 0 0 0 0 0 D3
11 (12) (A) INPUT 0 0 0 0 0 0 0 EINT0
43 (2) (A) INPUT 0 0 0 0 0 1 0 nGCS0
42 (1) (A) INPUT 0 0 0 0 0 5 0 nGCS1
2 (5) (A) INPUT 0 0 0 0 0 1 0 nGCS2
3 (6) (A) INPUT 0 0 0 0 0 3 0 nGCS3
5 (7) (A) INPUT 0 0 0 0 0 1 0 nGCS4
12 (13) (A) INPUT 0 0 0 0 0 4 0 nOE
39 - - INPUT 0 0 0 0 0 2 0 NRST
13 (14) (A) INPUT 0 0 0 0 0 4 0 nWE
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
h = Register powers up high
Device-Specific Information: c:\max2work\bus\7032_can.rpt
7032_can
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
28 23 B OUTPUT t 0 0 0 5 0 0 0 CANALE
34 18 B OUTPUT t 0 0 0 4 0 0 0 CANCS0
35 17 B OUTPUT t 0 0 0 5 0 0 0 CANRD
30 22 B OUTPUT t 0 0 0 5 0 0 0 CANWR
15 16 A OUTPUT t 0 0 0 1 0 0 0 DIR1
14 15 A OUTPUT t 0 0 0 5 0 0 0 nEXTBUS
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