📄 alphaops.h
字号:
#define GENTRAP_FUNC_STR "gentrap"
#define KBPT_FUNC_STR "kbpt"
#define CALLKD_FUNC_STR "callkd"
//
// Priveleged call pal functions.
//
#define HALT_FUNC (PRIV_PAL_FUNC | 0x00)
#define RESTART_FUNC (PRIV_PAL_FUNC | 0x01)
#define DRAINA_FUNC (PRIV_PAL_FUNC | 0x02)
#define REBOOT_FUNC (PRIV_PAL_FUNC | 0x03)
#define INITPAL_FUNC (PRIV_PAL_FUNC | 0x04)
#define WRENTRY_FUNC (PRIV_PAL_FUNC | 0x05)
#define SWPIRQL_FUNC (PRIV_PAL_FUNC | 0x06)
#define RDIRQL_FUNC (PRIV_PAL_FUNC | 0x07)
#define DI_FUNC (PRIV_PAL_FUNC | 0X08)
#define EI_FUNC (PRIV_PAL_FUNC | 0x09)
#define SWPPAL_FUNC (PRIV_PAL_FUNC | 0x0A)
#define SSIR_FUNC (PRIV_PAL_FUNC | 0x0C)
#define CSIR_FUNC (PRIV_PAL_FUNC | 0x0D)
#define RFE_FUNC (PRIV_PAL_FUNC | 0x0E)
#define RETSYS_FUNC (PRIV_PAL_FUNC | 0x0F)
#define SWPCTX_FUNC (PRIV_PAL_FUNC | 0x10)
#define SWPPROCESS_FUNC (PRIV_PAL_FUNC | 0x11)
#define RDMCES_FUNC (PRIV_PAL_FUNC | 0x12)
#define WRMCES_FUNC (PRIV_PAL_FUNC | 0x13)
#define TBIA_FUNC (PRIV_PAL_FUNC | 0x14)
#define TBIS_FUNC (PRIV_PAL_FUNC | 0x15)
#define DTBIS_FUNC (PRIV_PAL_FUNC | 0x16)
#define TBISASN_FUNC (PRIV_PAL_FUNC | 0x17)
#define RDKSP_FUNC (PRIV_PAL_FUNC | 0x18)
#define SWPKSP_FUNC (PRIV_PAL_FUNC | 0x19)
#define RDPSR_FUNC (PRIV_PAL_FUNC | 0x1A)
#define RDPCR_FUNC (PRIV_PAL_FUNC | 0x1C)
#define RDTHREAD_FUNC (PRIV_PAL_FUNC | 0x1E)
#define TBIM_FUNC (PRIV_PAL_FUNC | 0x20)
#define TBIMASN_FUNC (PRIV_PAL_FUNC | 0x21)
#define TBIM64_FUNC (PRIV_PAL_FUNC | 0x22)
#define TBIS64_FUNC (PRIV_PAL_FUNC | 0x23)
#define RDCOUNTERS_FUNC (PRIV_PAL_FUNC | 0x30)
#define RDSTATE_FUNC (PRIV_PAL_FUNC | 0x31)
#define WRPERFMON_FUNC (PRIV_PAL_FUNC | 0x32)
#define HALT_FUNC_STR "halt"
#define RESTART_FUNC_STR "restart"
#define DRAINA_FUNC_STR "draina"
#define REBOOT_FUNC_STR "reboot"
#define INITPAL_FUNC_STR "initpal"
#define WRENTRY_FUNC_STR "wrentry"
#define SWPIRQL_FUNC_STR "swpirql"
#define RDIRQL_FUNC_STR "rdirql"
#define DI_FUNC_STR "di"
#define EI_FUNC_STR "ei"
#define SWPPAL_FUNC_STR "swppal"
#define SSIR_FUNC_STR "ssir"
#define CSIR_FUNC_STR "csir"
#define RFE_FUNC_STR "rfe"
#define RETSYS_FUNC_STR "retsys"
#define SWPCTX_FUNC_STR "swpctx"
#define SWPPROCESS_FUNC_STR "swpprocess"
#define RDMCES_FUNC_STR "rdmces"
#define WRMCES_FUNC_STR "wrmces"
#define TBIA_FUNC_STR "tbia"
#define TBIS_FUNC_STR "tbis"
#define DTBIS_FUNC_STR "dtbis"
#define TBISASN_FUNC_STR "tbisasn"
#define RDKSP_FUNC_STR "rdksp"
#define SWPKSP_FUNC_STR "swpksp"
#define RDPSR_FUNC_STR "rdpsr"
#define RDPCR_FUNC_STR "rdpcr"
#define RDTHREAD_FUNC_STR "rdthread"
#define TBIM_FUNC_STR "tbim"
#define TBIMASN_FUNC_STR "tbimasn"
#define TBIM64_FUNC_STR "tbim64"
#define TBIS64_FUNC_STR "tbis64"
#define RDCOUNTERS_FUNC_STR "rdcounters"
#define RDSTATE_FUNC_STR "rdstate"
#define WRPERFMON_FUNC_STR "wrperfmon"
//
// 21064 (ev4) - specific call pal functions.
//
#define INITPCR_FUNC (PRIV_PAL_FUNC | 0x38)
#define INITPCR_FUNC_STR "initpcr"
//
// Type (10) EV4 MTPR/MFPR PAL mode instructions.
//
// 3 2 2 2 2 1 1
// 1 6 5 1 0 6 5 8 7 6 5 4 0
// +-----------+---------+---------+---------------+-+-+-+---------+
// | opcode | Ra | Rb | IGN |P|A|I| Index |
// +-----------+---------+---------+---------------+-+-+-+---------+
//
typedef struct _Alpha_EV4_PR_Format {
ULONG Index : 5;
ULONG Ibox : 1;
ULONG Abox : 1;
ULONG PalTemp : 1;
ULONG IGN : 8;
ULONG Rb : 5;
ULONG Ra : 5;
ULONG Opcode : 6;
} Alpha_EV4_PR_Format;
//
// Type (10) EV5 MTPR/MFPR PAL mode instructions.
//
// 3 2 2 2 2 1 1
// 1 6 5 1 0 6 5 0
// +-----------+---------+---------+-------------------------------+
// | opcode | Ra | Rb | Index |
// +-----------+---------+---------+-------------------------------+
//
typedef struct _Alpha_EV5_PR_Format {
ULONG Index : 16;
ULONG Rb : 5;
ULONG Ra : 5;
ULONG Opcode : 6;
} Alpha_EV5_PR_Format;
#define MTPR_OP 0x1D
#define MFPR_OP 0x19
#define MTPR_OP_STR "mt"
#define MFPR_OP_STR "mf"
//
// Type (11) EV4 special memory PAL mode access.
//
// 3 2 2 2 2 1 1 1 1 1 1
// 1 6 5 1 0 6 5 4 3 2 1 0
// +-----------+---------+---------+-+-+-+-+-----------------------+
// | opcode | Ra | Rb |P|A|R|Q| Disp |
// +-----------+---------+---------+-+-+-+-+-----------------------+
//
typedef struct _Alpha_EV4_MEM_Format {
ULONG Disp : 12;
ULONG QuadWord : 1;
ULONG RWcheck : 1;
ULONG Alt : 1;
ULONG Physical : 1;
ULONG Rb : 5;
ULONG Ra : 5;
ULONG Opcode : 6;
} Alpha_EV4_MEM_Format;
//
// Type (11) EV5 special memory PAL mode access.
//
// 3 2 2 2 2 1 1 1 1 1 1
// 1 6 5 1 0 6 5 4 3 2 1 0
// +-----------+---------+---------+-+-+-+-+-----------------------+
// | opcode | Ra | Rb |P|A|R|Q| Disp |
// +-----------+---------+---------+-+-+-+-+-----------------------+
//
typedef struct _Alpha_EV5_MEM_Format {
ULONG Disp : 10;
ULONG Lock_Cond: 1;
ULONG Vpte: 1;
ULONG QuadWord : 1;
ULONG RWcheck : 1;
ULONG Alt : 1;
ULONG Physical : 1;
ULONG Rb : 5;
ULONG Ra : 5;
ULONG Opcode : 6;
} Alpha_EV5_MEM_Format;
#define HWLD_OP 0x1B
#define HWST_OP 0x1F
#define HWLD_OP_STR "hwld"
#define HWST_OP_STR "hwst"
// Type (12) EV4 PAL mode switch.
//
// 3 2 2 2 2 1 1 1 1
// 1 6 5 1 0 6 5 4 3 0
// +-----------+---------+---------+-+-+---------------------------+
// | opcode | Ra | Rb |1|0| IGN |
// +-----------+---------+---------+-+-+---------------------------+
typedef struct _Alpha_EV4_REI_Format {
ULONG IGN : 14;
ULONG zero : 1;
ULONG one : 1;
ULONG Rb : 5;
ULONG Ra : 5;
ULONG Opcode : 6;
} Alpha_EV4_REI_Format;
// Type (12) EV5 PAL mode switch.
//
// 3 2 2 2 2 1 1 1 1
// 1 6 5 1 0 6 5 4 3 0
// +-----------+---------+---------+-+-+---------------------------+
// | opcode | Ra | Rb |1|0| IGN |
// +-----------+---------+---------+-+-+---------------------------+
typedef struct _Alpha_EV5_REI_Format {
ULONG IGN : 14;
ULONG Type: 2;
ULONG Rb : 5;
ULONG Ra : 5;
ULONG Opcode : 6;
} Alpha_EV5_REI_Format;
#define REI_OP 0x1E
#define REI_OP_STR "rei"
//
//
//
typedef union _Alpha_Instruction {
ULONG Long;
UCHAR Byte[4];
Alpha_Memory_Format Memory;
Alpha_Jump_Format Jump;
Alpha_Branch_Format Branch;
Alpha_OpReg_Format OpReg;
Alpha_OpLit_Format OpLit;
Alpha_FpOp_Format FpOp;
Alpha_PAL_Format Pal;
Alpha_EV4_PR_Format EV4_PR;
Alpha_EV4_MEM_Format EV4_MEM;
Alpha_EV4_REI_Format EV4_REI;
Alpha_EV5_PR_Format EV5_PR;
Alpha_EV5_MEM_Format EV5_MEM;
Alpha_EV5_REI_Format EV5_REI;
} ALPHA_INSTRUCTION, *PALPHA_INSTRUCTION;
//
// Define standard integer register assignments.
//
#define V0_REG 0 // v0 - return value register
#define T0_REG 1 // t0 - temporary register
#define T1_REG 2 // t1 - temporary register
#define T2_REG 3 // t2 - temporary register
#define T3_REG 4 // t3 - temporary register
#define T4_REG 5 // t4 - temporary register
#define T5_REG 6 // t5 - temporary register
#define T6_REG 7 // t6 - temporary register
#define T7_REG 8 // t7 - temporary register
#define S0_REG 9 // s0 - saved register
#define S1_REG 10 // s1 - saved register
#define S2_REG 11 // s2 - saved register
#define S3_REG 12 // s3 - saved register
#define S4_REG 13 // s4 - saved register
#define S5_REG 14 // s5 - saved register
#define S6_REG 15 // s6 - saved register, aka fp
#define FP_REG 15 // fp - frame pointer register
#define A0_REG 16 // a0 - argument register
#define A1_REG 17 // a1 - argument register
#define A2_REG 18 // a2 - argument register
#define A3_REG 19 // a3 - argument register
#define A4_REG 20 // a4 - argument register
#define A5_REG 21 // a5 - argument register
#define T8_REG 22 // t8 - temporary register
#define T9_REG 23 // t9 - temporary register
#define T10_REG 24 // t10 - temporary register
#define T11_REG 25 // t11 - temporary register
#define RA_REG 26 // ra - return address register
#define T12_REG 27 // t12 - temporary register
#define AT_REG 28 // at - assembler temporary register
#define GP_REG 29 // gp - global pointer register
#define SP_REG 30 // sp - stack pointer register
#define ZERO_REG 31 // zero - zero register
//
// Define standard floating point register assignments.
//
#define F0_REG 0 // floating return value register (real)
#define F1_REG 1 // floating return value register (imaginary)
#define F16_REG 16 // floating argument register
#define FZERO_REG 31 // floating zero register
//
// Define standard integer register strings
//
#define V0_REG_STR "v0" // - return value register
#define T0_REG_STR "t0" // - temporary register
#define T1_REG_STR "t1" // - temporary register
#define T2_REG_STR "t2" // - temporary register
#define T3_REG_STR "t3" // - temporary register
#define T4_REG_STR "t4" // - temporary register
#define T5_REG_STR "t5" // - temporary register
#define T6_REG_STR "t6" // - temporary register
#define T7_REG_STR "t7" // - temporary register
#define S0_REG_STR "s0" // - saved register
#define S1_REG_STR "s1" // - saved register
#define S2_REG_STR "s2" // - saved register
#define S3_REG_STR "s3" // - saved register
#define S4_REG_STR "s4" // - saved register
#define S5_REG_STR "s5" // - saved register
#define S6_REG_STR "s6" // - saved register, aka fp
#define FP_REG_STR "fp" // - frame pointer register
#define A0_REG_STR "a0" // - argument register
#define A1_REG_STR "a1" // - argument register
#define A2_REG_STR "a2" // - argument register
#define A3_REG_STR "a3" // - argument register
#define A4_REG_STR "a4" // - argument register
#define A5_REG_STR "a5" // - argument register
#define T8_REG_STR "t8" // - temporary register
#define T9_REG_STR "t9" // - temporary register
#define T10_REG_STR "t10" // - temporary register
#define T11_REG_STR "t11" // - temporary register
#define RA_REG_STR "ra" // - return address register
#define T12_REG_STR "t12" // - temporary register
#define AT_REG_STR "at" // - assembler temporary register
#define GP_REG_STR "gp" // - global pointer register
#define SP_REG_STR "sp" // - stack pointer register
#define ZERO_REG_STR "zero" // - zero register
//
// Define maximum and minimum single and double exponent values.
//
#define DOUBLE_MAXIMUM_EXPONENT 2047
#define DOUBLE_MINIMUM_EXPONENT 0
#define SINGLE_MAXIMUM_EXPONENT 255
#define SINGLE_MINIMUM_EXPONENT 0
//
// Define single and double exponent bias values.
//
#define SINGLE_EXPONENT_BIAS 127
#define DOUBLE_EXPONENT_BIAS 1023
//
// Define the largest single and double values.
//
#define SINGLE_MAXIMUM_VALUE 0x7f7fffff
#define DOUBLE_MAXIMUM_VALUE_HIGH 0x7fefffff
#define DOUBLE_MAXIMUM_VALUE_LOW 0xffffffff
//
// Define single and double quiet and signaling Nan values
// (these are identical to X86 formats; Mips is different).
//
#define SINGLE_QUIET_NAN_PREFIX 0x7fc00000
#define SINGLE_SIGNAL_NAN_PREFIX 0x7f800000
#define SINGLE_QUIET_NAN_VALUE 0xffc00000
#define DOUBLE_QUIET_NAN_PREFIX_HIGH 0x7ff80000
#define DOUBLE_SIGNAL_NAN_PREFIX_HIGH 0x7ff00000
#define DOUBLE_QUIET_NAN_VALUE_HIGH 0xfff80000
#define DOUBLE_QUIET_NAN_VALUE_LOW 0x0
//
// Define positive single and double infinity values.
//
#define SINGLE_INFINITY_VALUE 0x7f800000
#define DOUBLE_INFINITY_VALUE_HIGH 0x7ff00000
#define DOUBLE_INFINITY_VALUE_LOW 0x0
//
// Quadword versions of the above.
//
#define DOUBLE_MAXIMUM_VALUE ((ULONGLONG)0x7fefffffffffffff)
#define DOUBLE_INFINITY_VALUE ((ULONGLONG)0x7ff0000000000000)
#define DOUBLE_QUIET_NAN_VALUE ((ULONGLONG)0xfff8000000000000)
//
// Define result values for IEEE floating point comparison operations.
// True is 2.0 and False is 0.0.
//
#define FP_COMPARE_TRUE ((ULONGLONG)0x4000000000000000)
#define FP_COMPARE_FALSE ((ULONGLONG)0x0000000000000000)
//
// Define Alpha AXP rounding modes.
//
#define ROUND_TO_ZERO 0 // round toward zero
#define ROUND_TO_MINUS_INFINITY 1 // round toward minus infinity
#define ROUND_TO_NEAREST 2 // round to nearest representable value
#define ROUND_TO_PLUS_INFINITY 3 // round toward plus infinity
#endif // _ALPHAOPS_
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -