📄 alphaops.h
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/*++
Copyright (c) 1992-1996 Digital Equipment Corporation
Module Name:
alphaops.h
Abstract:
Alpha AXP instruction and floating constant definitions.
Author:
Revision History:
--*/
#ifndef _ALPHAOPS_
#define _ALPHAOPS_
//
// Instruction types.
// The Alpha architecture does not number the instruction types,
// this numbering is for software decoding only.
//
#define ALPHA_UNKNOWN 0 // Reserved or illegal
#define ALPHA_MEMORY 1 // Memory (load/store)
#define ALPHA_FP_MEMORY 2 // Floating point Memory
#define ALPHA_MEMSPC 3 // Memory special
#define ALPHA_JUMP 4 // Jump (memory formation)
#define ALPHA_BRANCH 5 // Branch
#define ALPHA_FP_BRANCH 6 // Floating Point Branch
#define ALPHA_OPERATE 7 // Register-register operate
#define ALPHA_LITERAL 8 // Literal-register operate
#define ALPHA_FP_OPERATE 9 // Floating point operate
#define ALPHA_FP_CONVERT 10 // Floating point convert
#define ALPHA_CALLPAL 11 // Call to PAL
#define ALPHA_EV4_PR 12 // EV4 MTPR/MFPR PAL mode instructions
#define ALPHA_EV4_MEM 13 // EV4 special memory PAL mode access
#define ALPHA_EV4_REI 14 // EV4 PAL mode switch
//
// Instruction Opcodes.
//
#define CALLPAL_OP 0x00 // ALPHA_CALLPAL
#define _01_OP 0x01 // - reserved opcode
#define _02_OP 0x02 // - reserved opcode
#define _03_OP 0x03 // - reserved opcode
#define _04_OP 0x04 // - reserved opcode
#define _05_OP 0x05 // - reserved opcode
#define _06_OP 0x06 // - reserved opcode
#define _07_OP 0x07 // - reserved opcode
#define _0A_OP 0x0A // - reserved opcode
#define _0C_OP 0x0C // - reserved opcode
#define _0D_OP 0x0D // - reserved opcode
#define _0E_OP 0x0E // - reserved opcode
#define _1C_OP 0x1C // - reserved opcode
#define LDA_OP 0x08 // ALPHA_MEMORY
#define LDAH_OP 0x09 // ALPHA_MEMORY
#define LDBU_OP 0x0A // ALPHA_MEMORY
#define LDQ_U_OP 0x0B // ALPHA_MEMORY
#define LDWU_OP 0x0C // ALPHA_MEMORY
#define STW_OP 0x0D // ALPHA_MEMORY
#define STB_OP 0x0E // ALPHA_MEMORY
#define STQ_U_OP 0x0F // ALPHA_MEMORY
#define ARITH_OP 0x10 // ALPHA_OPERATE or ALPHA_LITERAL
#define BIT_OP 0x11 // ALPHA_OPERATE or ALPHA_LITERAL
#define BYTE_OP 0x12 // ALPHA_OPERATE or ALPHA_LITERAL
#define MUL_OP 0x13 // ALPHA_OPERATE or ALPHA_LITERAL
#define _14_OP 0x14 // - reserved opcode
#define VAXFP_OP 0x15 // ALPHA_FP_OPERATE
#define IEEEFP_OP 0x16 // ALPHA_FP_OPERATE
#define FPOP_OP 0x17 // ALPHA_FP_OPERATE
#define MEMSPC_OP 0x18 // ALPHA_MEMORY
#define PAL19_OP 0x19 // - reserved for PAL mode
//#define MFPR_OP 0x19 // ALPHA_MFPR
#define JMP_OP 0x1A // ALPHA_JUMP
#define PAL1B_OP 0x1B // - reserved for PAL mode
#define SEXT_OP 0x1C // ALPHA_OPERATE
#define PAL1D_OP 0x1D // - reserved for PAL mode
//#define MTPR_OP 0x1D // ALPHA_MTPR
#define PAL1E_OP 0x1E // - reserved for PAL mode
#define PAL1F_OP 0x1F // - reserved for PAL mode
#define LDF_OP 0x20 // ALPHA_MEMORY
#define LDG_OP 0x21 // ALPHA_MEMORY
#define LDS_OP 0x22 // ALPHA_MEMORY
#define LDT_OP 0x23 // ALPHA_MEMORY
#define STF_OP 0x24 // ALPHA_MEMORY
#define STG_OP 0x25 // ALPHA_MEMORY
#define STS_OP 0x26 // ALPHA_MEMORY
#define STT_OP 0x27 // ALPHA_MEMORY
#define LDL_OP 0x28 // ALPHA_MEMORY
#define LDQ_OP 0x29 // ALPHA_MEMORY
#define LDL_L_OP 0x2A // ALPHA_MEMORY
#define LDQ_L_OP 0x2B // ALPHA_MEMORY
#define STL_OP 0x2C // ALPHA_MEMORY
#define STQ_OP 0x2D // ALPHA_MEMORY
#define STL_C_OP 0x2E // ALPHA_MEMORY
#define STQ_C_OP 0x2F // ALPHA_MEMORY
#define BR_OP 0x30 // ALPHA_BRANCH
#define FBEQ_OP 0x31 // ALPHA_BRANCH
#define FBLT_OP 0x32 // ALPHA_BRANCH
#define FBLE_OP 0x33 // ALPHA_BRANCH
#define BSR_OP 0x34 // ALPHA_BRANCH
#define FBNE_OP 0x35 // ALPHA_BRANCH
#define FBGE_OP 0x36 // ALPHA_BRANCH
#define FBGT_OP 0x37 // ALPHA_BRANCH
#define BLBC_OP 0x38 // ALPHA_BRANCH
#define BEQ_OP 0x39 // ALPHA_BRANCH
#define BLT_OP 0x3A // ALPHA_BRANCH
#define BLE_OP 0x3B // ALPHA_BRANCH
#define BLBS_OP 0x3C // ALPHA_BRANCH
#define BNE_OP 0x3D // ALPHA_BRANCH
#define BGE_OP 0x3E // ALPHA_BRANCH
#define BGT_OP 0x3F // ALPHA_BRANCH
#define LDA_OP_STR "lda"
#define LDAH_OP_STR "ldah"
#define LDBU_OP_STR "ldbu"
#define LDQ_U_OP_STR "ldq_u"
#define STQ_U_OP_STR "stq_u"
#define LDF_OP_STR "ldf"
#define LDG_OP_STR "ldg"
#define LDS_OP_STR "lds"
#define LDT_OP_STR "ldt"
#define LDWU_OP_STR "ldwu"
#define STF_OP_STR "stf"
#define STG_OP_STR "stg"
#define STS_OP_STR "sts"
#define STT_OP_STR "stt"
#define LDL_OP_STR "ldl"
#define LDQ_OP_STR "ldq"
#define LDL_L_OP_STR "ldl_l"
#define LDQ_L_OP_STR "ldq_l"
#define SEXT_OP_STR "sext"
#define STB_OP_STR "stb"
#define STL_OP_STR "stl"
#define STQ_OP_STR "stq"
#define STL_C_OP_STR "stl_c"
#define STQ_C_OP_STR "stq_c"
#define STW_OP_STR "stw"
#define BR_OP_STR "br"
#define FBEQ_OP_STR "fbeq"
#define FBLT_OP_STR "fblt"
#define FBLE_OP_STR "fble"
#define BSR_OP_STR "bsr"
#define FBNE_OP_STR "fbne"
#define FBGE_OP_STR "fbge"
#define FBGT_OP_STR "fbgt"
#define BLBC_OP_STR "blbc"
#define BEQ_OP_STR "beq"
#define BLT_OP_STR "blt"
#define BLE_OP_STR "ble"
#define BLBS_OP_STR "blbs"
#define BNE_OP_STR "bne"
#define BGE_OP_STR "bge"
#define BGT_OP_STR "bgt"
//
// Type (1) Memory Instruction Format.
// Type (2) Memory Special Instruction Format.
//
// 3 2 2 2 2 1 1
// 1 6 5 1 0 6 5 0
// +-----------+---------+---------+-------------------------------+
// | opcode | Ra | Rb | Memory_disp |
// +-----------+---------+---------+-------------------------------+
//
// LDAx Ra.wq,disp.ab(Rb.ab) x = (,H)
// LDx Ra.wq,disp.ab(Rb.ab) x = (L,Q,F,G,S,T)
// LDQ_U Ra.wq,disp.ab(Rb.ab)
// LDx_L Ra.wq,disp.ab(Rb.ab) x = (L,Q)
// STx_C Ra.mq,disp.ab(Rb.ab) x = (L,Q)
// STx Ra.rq,disp.ab(Rb.ab) x = (L,Q,F,G,S,T)
// STQ_U Ra.rq,disp.ab(Rb.ab)
//
typedef struct _Alpha_Memory_Format {
LONG MemDisp : 16;
ULONG Rb : 5;
ULONG Ra : 5;
ULONG Opcode : 6;
} Alpha_Memory_Format;
//
// Special Memory instruction function codes (in Memdisp).
//
#define TRAPB_FUNC 0x0000
#define EXCB_FUNC 0x0400
#define MB_FUNC 0x4000
#define WMB_FUNC 0x4400
#define MB2_FUNC 0x4800
#define MB3_FUNC 0x4C00
#define FETCH_FUNC 0x8000
#define FETCH_M_FUNC 0xA000
#define RPCC_FUNC 0xC000
#define RC_FUNC 0xE000
#define RS_FUNC 0xF000
#define TRAPB_FUNC_STR "trapb"
#define EXCB_FUNC_STR "excb"
#define MB_FUNC_STR "mb"
#define MB1_FUNC_STR "wmb"
#define MB2_FUNC_STR "mb2"
#define MB3_FUNC_STR "mb3"
#define FETCH_FUNC_STR "fetch"
#define FETCH_M_FUNC_STR "fetch_m"
#define RPCC_FUNC_STR "rpcc"
#define RC_FUNC_STR "rc"
#define RS_FUNC_STR "rs"
//
// Type (3) Memory Format Jump Instructions.
//
// 3 2 2 2 2 1 1 1 1
// 1 6 5 1 0 6 5 4 3 0
// +-----------+---------+---------+---+---------------------------+
// | opcode | Ra | Rb |Fnc| Hint |
// +-----------+---------+---------+---+---------------------------+
//
// xxx Ra.wq,(Rb.ab),hint xxx = (JMP, JSR, RET, JSR_COROUTINE)
//
typedef struct _Alpha_Jump_Format {
LONG Hint : 14;
ULONG Function : 2;
ULONG Rb : 5;
ULONG Ra : 5;
ULONG Opcode : 6;
} Alpha_Jump_Format;
//
// Jump function codes (in Function, opcode 1A, JMP_OP).
//
#define JMP_FUNC 0x0 // Jump
#define JSR_FUNC 0x1 // Jump to Subroutine
#define RET_FUNC 0x2 // Return from Subroutine
#define JSR_CO_FUNC 0x3 // Jump to Subroutine Return
#define JMP_FUNC_STR "jmp"
#define JSR_FUNC_STR "jsr"
#define RET_FUNC_STR "ret"
#define JSR_CO_FUNC_STR "jsr_coroutine"
//
// The exception handling compatible return instruction has a hint value
// of 0001. Define a macro that identifies these return instructions.
// The Rb register field is masked out since it is normally, but not
// required to be, RA_REG.
//
#define IS_RETURN_0001_INSTRUCTION(Instruction) \
(((Instruction) & 0xFFE0FFFF) == 0x6BE08001)
//
// Type (4) Branch Instruction Format.
//
// 3 2 2 2 2
// 1 6 5 1 0 0
// +-----------+---------+-----------------------------------------+
// | opcode | Ra | Branch_disp |
// +-----------+---------+-----------------------------------------+
//
// Bxx Ra.rq,disp.al x = (EQ,NE,LT,LE,GT,GE,LBC,LBS)
// BxR Ra.wq,disp.al x = (,S)
// FBxx Ra.rq,disp.al x = (EQ,NE,LT,LE,GT,GE)
//
typedef struct _Alpha_Branch_Format {
LONG BranchDisp : 21;
ULONG Ra : 5;
ULONG Opcode : 6;
} Alpha_Branch_Format;
//
// Type (5) Operate Register Instruction Format.
// Type (6) Operate Literal Instruction Format.
// bop = Rb.rq or #b.ib
//
// 3 2 2 2 2 1 1 1 1 1
// 1 6 5 1 0 6 5 3 2 1 5 4 0
// +-----------+---------+---------+-----+-+-------------+---------+
// | opcode | Ra | Rb | SBZ |0| function | Rc |
// +-----------+---------+---------+-----+-+-------------+---------+
// 3 2 2 2 2 1 1 1
// 1 6 5 1 0 3 2 1 5 4 0
// +-----------+---------+---------------+-+-------------+---------+
// | opcode | Ra | LIT |1| function | Rc |
// +-----------+---------+---------------+-+-------------+---------+
//
//
// ADDx Ra.rq,bop,Rc.wq /V x = (Q,L)
// SxADDy Ra.rq,bop,Rc.wq x = (4,8), y = (Q, L)
// CMPx Ra.rq,bop,Rc.wq x = (EQ,LT,LE,ULT,ULE)
// MULx Ra.rq,bop,Rc.wq /V x = (Q,L)
// UMULH Ra.rq,bop,Rc.wq
// SUBx Ra.rq,bop,Rc.wq /V x = (Q,L)
// SxSUBy Ra.rq,bop,Rc.wq x = (4,8), y = (Q, L)
// xxx Ra.rq,bop,Rc.wq xxx = (AND,BIS,XOR,BIC,ORNOT,EQV)
// CMOVxx Ra.rq,bop,Rc.wq xx = (EQ,NE,LT,LE,GT,GE,LBC,LBS)
// SxL Ra.rq,bop,Rc.wq x = (L,R)
// SRA Ra.rq,bop,Rc.wq
// CMPBGE Ra.rq,bop,Rc.wq
// EXTxx Ra.rq,bop,Rc.wq xx = (BL,WL,WH,LL,LH,WL,QH)
// INSxx Ra.rq,bop,Rc.wq xx = (BL,WL,WH,LL,LH,WL,QH)
// MSKxx Ra.rq,bop,Rc.wq xx = (BL,WL,WH,LL,LH,WL,QH)
// ZAPx Ra.rq,bop,Rc.wq x = (,NOT)
//
typedef struct _Alpha_OpReg_Format {
ULONG Rc : 5;
ULONG Function : 7;
ULONG RbvType : 1; // 0 for register format
ULONG SBZ : 3;
ULONG Rb : 5;
ULONG Ra : 5;
ULONG Opcode : 6;
} Alpha_OpReg_Format;
typedef struct _Alpha_OpLit_Format {
ULONG Rc : 5;
ULONG Function : 7;
ULONG RbvType : 1; // 1 for literal format
ULONG Literal : 8;
ULONG Ra : 5;
ULONG Opcode : 6;
} Alpha_OpLit_Format;
#define RBV_REGISTER_FORMAT 0
#define RBV_LITERAL_FORMAT 1
//
// Arithmetic operate function codes (in Function, Opcode 10, ARITH_OP).
//
#define ADDL_FUNC 0x00 // Add Longword
#define ADDLV_FUNC 0x40 // Add Longword, Integer Overflow Enable
#define S4ADDL_FUNC 0x02 // Scaled Add Longword by 4
#define S8ADDL_FUNC 0x12 // Scaled Add Longword by 8
#define ADDQ_FUNC 0x20 // Add Quadword
#define ADDQV_FUNC 0x60 // Add Quadword, Integer Overflow Enable
#define S4ADDQ_FUNC 0x22 // Scaled Add Quadword by 4
#define S8ADDQ_FUNC 0x32 // Scaled Add Quadword by 8
#define SUBL_FUNC 0x09 // Subtract Longword
#define SUBLV_FUNC 0x49 // Subtract Longword, Integer Overflow Enable
#define S4SUBL_FUNC 0x0B // Scaled Subtract Longword by 4
#define S8SUBL_FUNC 0x1B // Scaled Subtract Longword by 8
#define SUBQ_FUNC 0x29 // Subtract Quadword
#define SUBQV_FUNC 0x69 // Subtract Quadword, Integer Overflow Enable
#define S4SUBQ_FUNC 0x2B // Scaled Subtract Quadword by 4
#define S8SUBQ_FUNC 0x3B // Scaled Subtract Quadword by 8
#define CMPEQ_FUNC 0x2D // Compare Signed Quadword Equal
#define CMPLT_FUNC 0x4D // Compare Signed Quadword Less Than
#define CMPLE_FUNC 0x6D // Compare Signed Quadword Less Than or Equal
#define CMPULT_FUNC 0x1D // Compare Unsigned Quadword Less Than
#define CMPULE_FUNC 0x3D // Compare Unsigned Quadword Less Than or Equal
#define CMPBGE_FUNC 0x0F // Compare 8 Unsigned Bytes Greater Than or Equal
#define ADDL_FUNC_STR "addl"
#define ADDLV_FUNC_STR "addl/v"
#define S4ADDL_FUNC_STR "s4addl"
#define S8ADDL_FUNC_STR "s8addl"
#define ADDQ_FUNC_STR "addq"
#define ADDQV_FUNC_STR "addq/v"
#define S4ADDQ_FUNC_STR "s4addq"
#define S8ADDQ_FUNC_STR "s8addq"
#define SUBL_FUNC_STR "subl"
#define SUBLV_FUNC_STR "subl/v"
#define S4SUBL_FUNC_STR "s4subl"
#define S8SUBL_FUNC_STR "s8subl"
#define SUBQ_FUNC_STR "subq"
#define SUBQV_FUNC_STR "subq/v"
#define S4SUBQ_FUNC_STR "s4subq"
#define S8SUBQ_FUNC_STR "s8subq"
#define CMPEQ_FUNC_STR "cmpeq"
#define CMPLT_FUNC_STR "cmplt"
#define CMPLE_FUNC_STR "cmple"
#define CMPULT_FUNC_STR "cmpult"
#define CMPULE_FUNC_STR "cmpule"
#define CMPBGE_FUNC_STR "cmpbge"
//
// Bit and conditional operate function codes (in Function, Opcode 11, BIT_OP).
//
#define AND_FUNC 0x00 // Logical Product
#define BIC_FUNC 0x08 // Logical Product with Complement
#define BIS_FUNC 0x20 // Logical Sum (OR)
#define EQV_FUNC 0x48 // Logical Equivalence (XORNOT)
#define ORNOT_FUNC 0x28 // Logical Sum with Complement
#define XOR_FUNC 0x40 // Logical Difference
#define CMOVEQ_FUNC 0x24 // CMOVE if Register Equal to Zero
#define CMOVGE_FUNC 0x46 // CMOVE if Register Greater Than or Equal to Zero
#define CMOVGT_FUNC 0x66 // CMOVE if Register Greater Than Zero
#define CMOVLBC_FUNC 0x16 // CMOVE if Register Low Bit Clear
#define CMOVLBS_FUNC 0x14 // CMOVE if Register Low Bit Set
#define CMOVLE_FUNC 0x64 // CMOVE if Register Less Than or Equal to Zero
#define CMOVLT_FUNC 0x44 // CMOVE if Register Less Than Zero
#define CMOVNE_FUNC 0x26 // CMOVE if Register Not Equal to Zero
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