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C51 COMPILER V7.06 MAIN 12/25/2007 19:33:30 PAGE 1
C51 COMPILER V7.06, COMPILATION OF MODULE MAIN
OBJECT MODULE PLACED IN MAIN.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE MAIN.C OPTIMIZE(6,SIZE) BROWSE DEBUG OBJECTEXTEND CODE LISTINCLUDE SYMBOLS
stmt level source
1 /*------------------------------------------------------------------*-
2
3 Main.c (v1.00)
4
5 ------------------------------------------------------------------
6
7 DEMO PROGRAM FOR CAN SHARED-CLOCK SCHEDULER - Master
8
9 Required linker options (see Chapter 14 for details):
10
11 OVERLAY (main ~ (LED_Flash_Update,TRAFFIC_LIGHTS_Update),
12 SCH_Dispatch_Tasks ! (LED_Flash_Update,TRAFFIC_LIGHTS_Update))
13
14
15 COPYRIGHT
16 ---------
17
18 This code is from the book:
19
20 PATTERNS FOR TIME-TRIGGERED EMBEDDED SYSTEMS by Michael J. Pont
21 [Pearson Education, 2001; ISBN: 0-201-33138-1].
22
23 This code is copyright (c) 2001 by Michael J. Pont.
24
25 See book for copyright details and other information.
26
27 -*------------------------------------------------------------------*/
28
29 #include "Main.h"
1 =1 /*------------------------------------------------------------------*-
2 =1
3 =1 Main.H (v1.00)
4 =1
5 =1 ------------------------------------------------------------------
6 =1
7 =1 'Project Header' (see Chap 9) for project SCU_Cb (see Chap 27)
8 =1
9 =1
10 =1 COPYRIGHT
11 =1 ---------
12 =1
13 =1 This code is from the book:
14 =1
15 =1 PATTERNS FOR TIME-TRIGGERED EMBEDDED SYSTEMS by Michael J. Pont
16 =1 [Pearson Education, 2001; ISBN: 0-201-33138-1].
17 =1
18 =1 This code is copyright (c) 2001 by Michael J. Pont.
19 =1
20 =1 See book for copyright details and other information.
21 =1
22 =1 -*------------------------------------------------------------------*/
23 =1
24 =1 #ifndef _MAIN_H
25 =1 #define _MAIN_H
26 =1
C51 COMPILER V7.06 MAIN 12/25/2007 19:33:30 PAGE 2
27 =1 //------------------------------------------------------------------
28 =1 // WILL NEED TO EDIT THIS SECTION FOR EVERY PROJECT
29 =1 //------------------------------------------------------------------
30 =1
31 =1 // Must include the appropriate microcontroller header file here
32 =1 #include <reg515c.h>
1 =2 /*------------------------------------------------------------------
2 =2 REG515C.H
3 =2
4 =2 Header file for the Infineon C515C
5 =2 Copyright (c) 1988-2002 Keil Elektronik GmbH and Keil Software, Inc.
6 =2 All rights reserved.
7 =2 --------------------------------------------------------------------------*/
8 =2
9 =2 #ifndef __REG515C_H__
10 =2 #define __REG515C_H__
11 =2
12 =2 /* BYTE Registers */
13 =2 /* CPU */
14 =2 sfr ACC = 0xE0;
15 =2 sfr B = 0xF0;
16 =2 sfr DPL = 0x82;
17 =2 sfr DPH = 0x83;
18 =2 sfr DPSEL = 0x92;
19 =2 sfr PSW = 0xD0;
20 =2 sfr SP = 0x81;
21 =2 sfr SYSCON = 0xB1;
22 =2
23 =2 /* A/D Converter */
24 =2 sfr ADCON0 = 0xD8;
25 =2 sfr ADDATH = 0xD9;
26 =2 sfr ADDATL = 0xDA; /* in mapped SFR area */
27 =2 sfr ADCON1 = 0xDC;
28 =2
29 =2 /* Interrupt System */
30 =2 sfr IEN0 = 0xA8;
31 =2 sfr IEN1 = 0xB8;
32 =2 sfr IEN2 = 0x9A;
33 =2 sfr IP0 = 0xA9;
34 =2 sfr IP1 = 0xB9;
35 =2 sfr IRCON = 0xC0;
36 =2
37 =2 /* XRAM */
38 =2 sfr XPAGE = 0x91;
39 =2
40 =2 /* Ports */
41 =2 sfr P0 = 0x80;
42 =2 sfr P1 = 0x90;
43 =2 sfr P2 = 0xA0;
44 =2 sfr P3 = 0xB0;
45 =2 sfr P4 = 0xE8;
46 =2 sfr P5 = 0xF8;
47 =2 sfr DIR5 = 0xF8; /* in mapped SFR area */
48 =2 sfr P6 = 0xDB;
49 =2 sfr P7 = 0xFA;
50 =2
51 =2 /* Serial Channel */
52 =2 sfr SCON = 0x98;
53 =2 sfr SBUF = 0x99;
54 =2 sfr SRELL = 0xAA;
55 =2 sfr SRELH = 0xBA;
56 =2
C51 COMPILER V7.06 MAIN 12/25/2007 19:33:30 PAGE 3
57 =2 /* SSC Interface */
58 =2 sfr SSCCON = 0x93;
59 =2 sfr STB = 0x94;
60 =2 sfr SRB = 0x95;
61 =2 sfr SCF = 0xAB;
62 =2 sfr SCIEN = 0xAC;
63 =2 sfr SSCMOD = 0x96;
64 =2
65 =2 /* Timer0 / Timer1 */
66 =2 sfr TCON = 0x88;
67 =2 sfr TMOD = 0x89;
68 =2 sfr TL0 = 0x8A;
69 =2 sfr TL1 = 0x8B;
70 =2 sfr TH0 = 0x8C;
71 =2 sfr TH1 = 0x8D;
72 =2
73 =2 /* CAP/COM Unit / Timer2 */
74 =2 sfr CCEN = 0xC1;
75 =2 sfr CCL1 = 0xC2;
76 =2 sfr CCH1 = 0xC3;
77 =2 sfr CCL2 = 0xC4;
78 =2 sfr CCH2 = 0xC5;
79 =2 sfr CCL3 = 0xC6;
80 =2 sfr CCH3 = 0xC7;
81 =2 sfr T2CON = 0xC8;
82 =2 sfr CRCL = 0xCA;
83 =2 sfr CRCH = 0xCB;
84 =2 sfr TL2 = 0xCC;
85 =2 sfr TH2 = 0xCD;
86 =2
87 =2 /* Watchdog */
88 =2 sfr WDTREL = 0x86;
89 =2
90 =2 /* Power Save Moders */
91 =2 sfr PCON = 0x87;
92 =2 sfr PCON1 = 0x88; /* in mapped SFR area */
93 =2
94 =2
95 =2 /* BIT Register */
96 =2 /* PSW */
97 =2 sbit CY = PSW^7;
98 =2 sbit AC = PSW^6;
99 =2 sbit F0 = PSW^5;
100 =2 sbit RS1 = PSW^4;
101 =2 sbit RS0 = PSW^3;
102 =2 sbit OV = PSW^2;
103 =2 sbit F1 = PSW^1;
104 =2 sbit P = PSW^0;
105 =2
106 =2 /* TCON */
107 =2 sbit TF1 = TCON^7;
108 =2 sbit TR1 = TCON^6;
109 =2 sbit TF0 = TCON^5;
110 =2 sbit TR0 = TCON^4;
111 =2 sbit IE1 = TCON^3;
112 =2 sbit IT1 = TCON^2;
113 =2 sbit IE0 = TCON^1;
114 =2 sbit IT0 = TCON^0;
115 =2
116 =2 /* IEN0 */
117 =2 sbit EAL = IEN0^7;
118 =2 sbit WDT = IEN0^6;
C51 COMPILER V7.06 MAIN 12/25/2007 19:33:30 PAGE 4
119 =2 sbit ET2 = IEN0^5;
120 =2 sbit ES = IEN0^4;
121 =2 sbit ET1 = IEN0^3;
122 =2 sbit EX1 = IEN0^2;
123 =2 sbit ET0 = IEN0^1;
124 =2 sbit EX0 = IEN0^0;
125 =2
126 =2 /* IEN1 */
127 =2 sbit EXEN2 = IEN1^7;
128 =2 sbit SWDT = IEN1^6;
129 =2 sbit EX6 = IEN1^5;
130 =2 sbit EX5 = IEN1^4;
131 =2 sbit EX4 = IEN1^3;
132 =2 sbit EX3 = IEN1^2;
133 =2 sbit EX2 = IEN1^1;
134 =2 sbit EADC = IEN1^0;
135 =2
136 =2 /* P3 */
137 =2 sbit RD = P3^7;
138 =2 sbit WR = P3^6;
139 =2 sbit T1 = P3^5;
140 =2 sbit T0 = P3^4;
141 =2 sbit INT1 = P3^3;
142 =2 sbit INT0 = P3^2;
143 =2 sbit TXD = P3^1;
144 =2 sbit RXD = P3^0;
145 =2
146 =2 /* SCON */
147 =2 sbit SM0 = SCON^7;
148 =2 sbit SM1 = SCON^6;
149 =2 sbit SM2 = SCON^5;
150 =2 sbit REN = SCON^4;
151 =2 sbit TB8 = SCON^3;
152 =2 sbit RB8 = SCON^2;
153 =2 sbit TI = SCON^1;
154 =2 sbit RI = SCON^0;
155 =2
156 =2 /* T2CON */
157 =2 sbit T2PS = T2CON^7;
158 =2 sbit I3FR = T2CON^6;
159 =2 sbit I2FR = T2CON^5;
160 =2 sbit T2R1 = T2CON^4;
161 =2 sbit T2R0 = T2CON^3;
162 =2 sbit T2CM = T2CON^2;
163 =2 sbit T2I1 = T2CON^1;
164 =2 sbit T2I0 = T2CON^0;
165 =2
166 =2 /* ADCON0 */
167 =2 sbit BD = ADCON0^7;
168 =2 sbit CLK = ADCON0^6;
169 =2 sbit ADEX = ADCON0^5;
170 =2 sbit BSY = ADCON0^4;
171 =2 sbit ADM = ADCON0^3;
172 =2 sbit MX2 = ADCON0^2;
173 =2 sbit MX1 = ADCON0^1;
174 =2 sbit MX0 = ADCON0^0;
175 =2
176 =2 /* IRCON */
177 =2 sbit EXF2 = IRCON^7;
178 =2 sbit TF2 = IRCON^6;
179 =2 sbit IEX6 = IRCON^5;
180 =2 sbit IEX5 = IRCON^4;
C51 COMPILER V7.06 MAIN 12/25/2007 19:33:30 PAGE 5
181 =2 sbit IEX4 = IRCON^3;
182 =2 sbit IEX3 = IRCON^2;
183 =2 sbit IEX2 = IRCON^1;
184 =2 sbit IADC = IRCON^0;
185 =2
186 =2 /* P1 */
187 =2 sbit T2 = P1^7;
188 =2 sbit CLKOUT = P1^6;
189 =2 sbit T2EX = P1^5;
190 =2 sbit INT2 = P1^4;
191 =2 sbit INT6 = P1^3;
192 =2 sbit INT5 = P1^2;
193 =2 sbit INT4 = P1^1;
194 =2 sbit INT3 = P1^0;
195 =2
196 =2 /* P4 */
197 =2 sbit RXDC = P4^7;
198 =2 sbit TXDC = P4^6;
199 =2 sbit INT8 = P4^5;
200 =2 sbit SLS = P4^4;
201 =2 sbit STO = P4^3;
202 =2 sbit SRI = P4^2;
203 =2 sbit SCLK = P4^1;
204 =2 sbit ADST = P4^0;
205 =2
206 =2 #endif
33 =1
34 =1 // Include oscillator / chip details here
35 =1 // (essential if generic delays / timeouts are used)
36 =1 // -
37 =1 // Oscillator / resonator frequency (in Hz) e.g. (11059200UL)
38 =1 #define OSC_FREQ (10000000UL)
39 =1
40 =1 // Number of oscillations per instruction (4, 6 or 12)
41 =1 // 12 - Original 8051 / 8052 and numerous modern versions
42 =1 // 6 - Various Infineon and Philips devices, etc.
43 =1 // 4 - Dallas, etc.
44 =1 //
45 =1 // Take care with Dallas devices
46 =1 // - Timers default to *12* osc ticks unless CKCON is modified
47 =1 // - If using generic code on a Dallas device, use 12 here
48 =1 #define OSC_PER_INST (6)
49 =1
50 =1 //------------------------------------------------------------------
51 =1 // SHOULD NOT NEED TO EDIT THE SECTIONS BELOW
52 =1 //------------------------------------------------------------------
53 =1 typedef unsigned char tByte;
54 =1 typedef unsigned int tWord;
55 =1 typedef unsigned long tLong;
56 =1
57 =1 // Misc #defines
58 =1 #ifndef TRUE
59 =1 #define FALSE 0
60 =1 #define TRUE (!FALSE)
61 =1 #endif
62 =1
63 =1 #define RETURN_NORMAL (bit) 0
64 =1 #define RETURN_ERROR (bit) 1
65 =1
66 =1
67 =1 //------------------------------------------------------------------
68 =1 // Interrupts
C51 COMPILER V7.06 MAIN 12/25/2007 19:33:30 PAGE 6
69 =1 // - see Chapter 13.
70 =1 //------------------------------------------------------------------
71 =1
72 =1 // Generic 8051/52 timer interrupts (used in most schedulers)
73 =1 #define INTERRUPT_Timer_0_Overflow 1
74 =1 #define INTERRUPT_Timer_1_Overflow 3
75 =1 #define INTERRUPT_Timer_2_Overflow 5
76 =1
77 =1 // Additional interrupts (used in shared-clock schedulers)
78 =1 #define INTERRUPT_EXTERNAL_0 0
79 =1 #define INTERRUPT_EXTERNAL_1 2
80 =1 #define INTERRUPT_UART_Rx_Tx 4
81 =1 #define INTERRUPT_CAN_c515c 17
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