tte.vhd

译码器的逻辑功能是将已赋予特定含义的一组二进制输入代码的原意"翻译"出来,变成对应的输出高低电平信号.该程序为3-8译码器.基于VHDL,其开发环境是MAXPLUS2.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TTE IS 
PORT(
     A,B,C,EN:IN STD_LOGIC;
     Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7:OUT STD_LOGIC
    );
END TTE;

ARCHITECTURE A OF TTE IS 
SIGNAL S:STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL SOUT:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
S<=A&B&C;
PROCESS(EN,S)
   BEGIN
       IF EN='0' THEN 
            SOUT<="00000000";
       ELSE
           CASE S IS 
                WHEN "000" => SOUT<="00000001";
                WHEN "001" => SOUT<="00000010";
                WHEN "010" => SOUT<="00000100";
                WHEN "011" => SOUT<="00001000";
                WHEN "100" => SOUT<="00010000";
                WHEN "101" => SOUT<="00100000";
                WHEN "110" => SOUT<="01000000";
                WHEN OTHERS => SOUT<="10000000";
           END CASE;
       END IF ;
   END PROCESS;
Y0<=SOUT(0);
Y1<=SOUT(1);
Y2<=SOUT(2);
Y3<=SOUT(3);
Y4<=SOUT(4);
Y5<=SOUT(5);
Y6<=SOUT(6);
Y7<=SOUT(7);
END A;