📄 clk_div5.tan.rpt
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Timing Analyzer report for clk_div5
Mon May 28 16:37:42 2007
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. Clock Hold: 'clk'
7. tco
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-----------+----------------------------------+------------------------------------------------+-----------+---------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-----------+----------------------------------+------------------------------------------------+-----------+---------+------------+----------+--------------+
; Worst-case tco ; N/A ; None ; 7.050 ns ; levelr ; clk_div ; clk ; -- ; 0 ;
; Clock Setup: 'clk' ; 48.401 ns ; 20.00 MHz ( period = 50.000 ns ) ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; countr[0] ; levelr ; clk ; clk ; 0 ;
; Clock Hold: 'clk' ; 1.047 ns ; 20.00 MHz ( period = 50.000 ns ) ; N/A ; levelf ; levelf ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-----------+----------------------------------+------------------------------------------------+-----------+---------+------------+----------+--------------+
+-------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+-----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+-----+-------------+
; Device Name ; EP1C3T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Clock Settings ; clk ; ; clk ; ;
+-------------------------------------------------------+--------------------+------+-----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; clk ; User Pin ; 20.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-----------+-----------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------+-----------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 48.401 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countr[0] ; levelr ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.338 ns ;
; 48.429 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countf[2] ; levelf ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.310 ns ;
; 48.564 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countr[1] ; countr[2] ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.175 ns ;
; 48.564 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countr[1] ; countr[0] ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.175 ns ;
; 48.565 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countf[0] ; countf[2] ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.174 ns ;
; 48.566 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countf[0] ; countf[0] ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.173 ns ;
; 48.567 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countr[1] ; levelr ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.172 ns ;
; 48.567 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countr[1] ; countr[1] ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.172 ns ;
; 48.567 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countf[0] ; levelf ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.172 ns ;
; 48.567 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countf[0] ; countf[1] ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.172 ns ;
; 48.656 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countr[0] ; countr[1] ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.083 ns ;
; 48.658 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countf[1] ; levelf ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.081 ns ;
; 48.658 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countf[1] ; countf[1] ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.081 ns ;
; 48.658 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countf[1] ; countf[0] ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.081 ns ;
; 48.658 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countf[1] ; countf[2] ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.081 ns ;
; 48.662 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countr[0] ; countr[0] ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.077 ns ;
; 48.664 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countr[0] ; countr[2] ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.075 ns ;
; 48.674 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; levelr ; levelr ; clk ; clk ; 50.000 ns ; 49.739 ns ; 1.065 ns ;
; 48.859 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countr[2] ; levelr ; clk ; clk ; 50.000 ns ; 49.739 ns ; 0.880 ns ;
; 48.863 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countf[2] ; countf[0] ; clk ; clk ; 50.000 ns ; 49.739 ns ; 0.876 ns ;
; 48.864 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countr[2] ; countr[0] ; clk ; clk ; 50.000 ns ; 49.739 ns ; 0.875 ns ;
; 48.866 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countr[2] ; countr[2] ; clk ; clk ; 50.000 ns ; 49.739 ns ; 0.873 ns ;
; 48.870 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; countf[2] ; countf[2] ; clk ; clk ; 50.000 ns ; 49.739 ns ; 0.869 ns ;
; 48.901 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; levelf ; levelf ; clk ; clk ; 50.000 ns ; 49.739 ns ; 0.838 ns ;
+-----------+-----------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'clk' ;
+---------------+-----------+-----------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+---------------+-----------+-----------+------------+----------+----------------------------+----------------------------+--------------------------+
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