lift.fit.qmsg

用fpga控制电梯,实现五层电梯的升降控制,运用vhdl编辑程序.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 17 22:19:44 2007 " "Info: Processing started: Mon Dec 17 22:19:44 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off lift -c lift " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off lift -c lift" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "lift EP1S10F484C5 " "Info: Automatically selected device EP1S10F484C5 for design lift" {  } {  } 0 0 "Automatically selected device %2!s! for design %1!s!" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20F484C5 " "Info: Device EP1S20F484C5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "20 20 " "Info: No exact pin location assignment(s) for 20 pins of 20 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "lamp " "Info: Pin lamp not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 14 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "lamp" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { lamp } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { lamp } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "run_wait\[0\] " "Info: Pin run_wait\[0\] not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 15 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "run_wait\[0\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { run_wait[0] } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { run_wait[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "run_wait\[1\] " "Info: Pin run_wait\[1\] not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 15 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "run_wait\[1\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { run_wait[1] } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { run_wait[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "run_wait\[2\] " "Info: Pin run_wait\[2\] not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 15 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "run_wait\[2\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { run_wait[2] } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { run_wait[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "run_wait\[3\] " "Info: Pin run_wait\[3\] not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 15 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "run_wait\[3\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { run_wait[3] } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { run_wait[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "st_out\[0\] " "Info: Pin st_out\[0\] not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 16 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "st_out\[0\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { st_out[0] } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { st_out[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "st_out\[1\] " "Info: Pin st_out\[1\] not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 16 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "st_out\[1\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { st_out[1] } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { st_out[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "st_out\[2\] " "Info: Pin st_out\[2\] not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 16 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "st_out\[2\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { st_out[2] } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { st_out[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "st_out\[3\] " "Info: Pin st_out\[3\] not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 16 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "st_out\[3\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { st_out[3] } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { st_out[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "direct\[0\] " "Info: Pin direct\[0\] not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 17 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "direct\[0\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { direct[0] } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { direct[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "direct\[1\] " "Info: Pin direct\[1\] not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 17 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "direct\[1\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { direct[1] } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { direct[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "direct\[2\] " "Info: Pin direct\[2\] not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 17 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "direct\[2\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { direct[2] } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { direct[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "direct\[3\] " "Info: Pin direct\[3\] not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 17 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "direct\[3\]" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { direct[3] } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { direct[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "run_stop " "Info: Pin run_stop not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 13 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "run_stop" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { run_stop } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { run_stop } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "close " "Info: Pin close not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 11 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "close" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { close } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { close } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "delay " "Info: Pin delay not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 12 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "delay" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { delay } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { delay } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "clkin " "Info: Pin clkin not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 7 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "clkin" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { clkin } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { clkin } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "st_ch " "Info: Pin st_ch not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 10 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "st_ch" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { st_ch } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { st_ch } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "downin " "Info: Pin downin not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 9 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "downin" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { downin } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { downin } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "upin " "Info: Pin upin not assigned to an exact location on the device" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 8 -1 0 } } { "d:/bin/Assignment Editor.qase" "" { Assignment "d:/bin/Assignment Editor.qase" 1 { { 0 "upin" } } } } { "d:/bin/Report_Window_01.qrpt" "" { Report "d:/bin/Report_Window_01.qrpt" "Compiler" "lift" "UNKNOWN" "V1" "D:/fpga例子/lift/db/lift.quartus_db" { Floorplan "D:/fpga例子/lift/" "" "" { upin } "NODE_NAME" } "" } } { "D:/fpga例子/lift/lift.fld" "" { Floorplan "D:/fpga例子/lift/lift.fld" "" "" { upin } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clkin Global clock in PIN L2 " "Info: Automatically promoted signal \"clkin\" to use Global clock in PIN L2" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 7 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "dir\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"dir\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "direct\[0\] " "Info: Destination \"direct\[0\]\" may be non-global or may not use global clock" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 17 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "dir\[0\] " "Info: Destination \"dir\[0\]\" may be non-global or may not use global clock" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 40 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "dir\[1\] " "Info: Destination \"dir\[1\]\" may be non-global or may not use global clock" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 40 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "add~263 " "Info: Destination \"add~263\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "dir\[2\] " "Info: Destination \"dir\[2\]\" may be non-global or may not use global clock" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 40 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "add~264 " "Info: Destination \"add~264\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "add~265 " "Info: Destination \"add~265\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "p2~2634 " "Info: Destination \"p2~2634\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "p2~2636 " "Info: Destination \"p2~2636\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "p2~2640 " "Info: Destination \"p2~2640\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 40 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}