lift.map.qmsg

用fpga控制电梯,实现五层电梯的升降控制,运用vhdl编辑程序.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 17 22:19:38 2007 " "Info: Processing started: Mon Dec 17 22:19:38 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lift -c lift " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lift -c lift" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lift.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lift.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lift-lift_arch " "Info: Found design unit 1: lift-lift_arch" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 21 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lift " "Info: Found entity 1: lift" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "lift " "Info: Elaborating entity \"lift\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "delayx lift.vhd(27) " "Warning (10036): Verilog HDL or VHDL warning at lift.vhd(27): object \"delayx\" assigned a value but never read" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 27 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ur lift.vhd(48) " "Warning (10631): VHDL Process Statement warning at lift.vhd(48): signal or variable \"ur\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"ur\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "dr lift.vhd(48) " "Warning (10631): VHDL Process Statement warning at lift.vhd(48): signal or variable \"dr\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"dr\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "ladd lift.vhd(65) " "Warning (10631): VHDL Process Statement warning at lift.vhd(65): signal or variable \"ladd\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"ladd\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: signal or variable \"%1!s!\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"%1!s!\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "divide lift.vhd(104) " "Warning (10492): VHDL Process Statement warning at lift.vhd(104): signal \"divide\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 104 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "divide dir\[0\] " "Info: Duplicate register \"divide\" merged to single register \"dir\[0\]\"" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 25 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ladd\[1\] " "Warning: Latch ladd\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA rtl~0 " "Warning: Ports D and ENA on the latch are fed by the same signal rtl~0" {  } {  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ur\[1\] " "Warning: Latch ur\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA p2~0 " "Warning: Ports D and ENA on the latch are fed by the same signal p2~0" {  } {  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ur\[2\] " "Warning: Latch ur\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA p2~0 " "Warning: Ports D and ENA on the latch are fed by the same signal p2~0" {  } {  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ur\[5\] " "Warning: Latch ur\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA p2~0 " "Warning: Ports D and ENA on the latch are fed by the same signal p2~0" {  } {  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ur\[6\] " "Warning: Latch ur\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA p2~0 " "Warning: Ports D and ENA on the latch are fed by the same signal p2~0" {  } {  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ur\[3\] " "Warning: Latch ur\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA p2~0 " "Warning: Ports D and ENA on the latch are fed by the same signal p2~0" {  } {  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ur\[4\] " "Warning: Latch ur\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA p2~0 " "Warning: Ports D and ENA on the latch are fed by the same signal p2~0" {  } {  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 48 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "ladd\[0\] " "Warning: Latch ladd\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA liftor\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal liftor\[2\]" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 104 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0}  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 65 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "run_wait\[3\] GND " "Warning: Pin \"run_wait\[3\]\" stuck at GND" {  } { { "lift.vhd" "" { Text "D:/fpga例子/lift/lift.vhd" 15 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "97 " "Info: Implemented 97 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "77 " "Info: Implemented 77 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 23 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 23 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 17 22:19:42 2007 " "Info: Processing ended: Mon Dec 17 22:19:42 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}