📄 gpifburst8a.lst
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474 4 GPIFTRIG = GPIFTRIGRD | GPIF_EP8; // R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s)
475 4 *EP0BUF = 0xA8; // return that there was a buffer available
476 4 BLINK_LED();
477 4 }
478 3 else
479 3 { // If EP busy then host is behind...
480 4 *EP0BUF = 0x00; // Buffer space wasn't available and we still have
481 4 // two buffers containing data
482 4 ledX_rdvar = LED3_ON; // Indicate buffer is not available
483 4 }
484 3 EP0BCH = 0;
485 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
486 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
487 3 break;
488 3 }
489 2 case VX_A9:
C51 COMPILER V6.10 GPIFBURST8A 06/27/2006 22:34:28 PAGE 9
490 2 { // Do a FIFO Wr transaction w/TC=BC from EP2
491 3 if( EP24FIFOFLGS & 0x02 )
492 3 { // EP2EF=1 when FIFO is empty, 8051 didn't "pass-on" pkt.
493 4 *EP0BUF = 0x00; // Buffer was empty, not available
494 4 ledX_rdvar = LED3_ON; // Indicate empty buffer while GPIF write transaction
495 4 }
496 3 else
497 3 { // EP2EF=0 when FIFO "not" empty, 8051 committed pkt.
498 4 GPIFTRIG = GPIF_EP2; // R/W=0, EP[1:0]=FIFO_EpNum for EPx write(s)
499 4 *EP0BUF = 0xA9;
500 4 BLINK_LED(); // Succesful transaction
501 4 }
502 3 EP0BCH = 0;
503 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
504 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
505 3 break;
506 3 }
507 2 case VX_AA:
508 2 { // manually commit IN data to host...
509 3 // GPIF needs to still be pointing to EP8, last FIFO accessed
510 3 if( EP2468STAT & 0x80 )
511 3 { // EP8F=1 when buffer is not available
512 4 *EP0BUF = 0x00; // buffer wasn't available
513 4 ledX_rdvar = LED3_ON; // debug
514 4 }
515 3 else
516 3 { // EP8F=0 when buffer is available
517 4 EP8BCH = EP8FIFOBCH;
518 4 EP8BCL = EP8FIFOBCL; // 8051 commits pkt by writing bc
519 4 ledX_rdvar = LED3_OFF; // debug
520 4 *EP0BUF = 0xAA;
521 4 }
522 3 EP0BCH = 0;
523 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
524 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
525 3 BLINK_LED();
526 3 break;
527 3 }
528 2 case VX_AB:
529 2 { // manually commit OUT data to master...
530 3 // GPIF needs to still be pointing to EP8, last FIFO accessed
531 3 if( EP2468STAT & 0x01 )
532 3 { // EP2EF=1 when FIFO is empty, host didn't sent pkt.
533 4 *EP0BUF = 0x00; // buffer was empty, not available
534 4 ledX_rdvar = LED3_ON; // debug
535 4 }
536 3 else
537 3 { // EP2EF=0 when FIFO "not" empty, host sent pkt.
538 4 EP2GPIFTCH = EP2BCH; // setup transaction count
539 4 EP2GPIFTCL = EP2BCL; // set EP2GPIFTC = EP2BC
540 4 EP2BCL = 0x00; // AUTOOUT=0, so "pass-on" pkt. to master (GPIF)
541 4 // once master xfr's OUT pkt, it "auto" (re)arms
542 4 // trigger FIFO write transaction(s), using SFR
543 4 *EP0BUF = 0xAB;
544 4 }
545 3 EP0BCH = 0;
546 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
547 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
548 3 BLINK_LED();
549 3 break;
550 3 }
551 2 case VX_AC:
C51 COMPILER V6.10 GPIFBURST8A 06/27/2006 22:34:28 PAGE 10
552 2 { // manually commit IN data to host...
553 3 // GPIF needs to still be pointing to EP8, last FIFO accessed
554 3 if( EP2468STAT & 0x80 )
555 3 { // EP8F=1 when buffer is not available
556 4 *EP0BUF = 0x00; // buffer wasn't available
557 4 ledX_rdvar = LED3_ON; // debug
558 4 }
559 3 else
560 3 { // EP8F=0 when buffer is available
561 4 INPKTEND = 0x08; // 8051 commits pkt by writing #8 to INPKTEND
562 4 *EP0BUF = 0xAC;
563 4 ledX_rdvar = LED3_OFF; // debug
564 4 }
565 3 EP0BCH = 0;
566 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
567 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
568 3 BLINK_LED();
569 3 break;
570 3 }
571 2 case VX_AD:
572 2 { // setup GPIF FIFO Reads w/TC=8
573 3 *EP0BUF = 0xAD;
574 3 EP8GPIFTCH = 0x00; // setup transaction count
575 3 EP8GPIFTCL = 0x08; // EP8GPIFTC = 8
576 3 EP0BCH = 0;
577 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
578 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
579 3 BLINK_LED();
580 3 break;
581 3 }
582 2 case VX_AE:
583 2 { // get status of GPIF
584 3 *EP0BUF = GPIFTRIG; // return status of GPIFDONE bit
585 3 EP0BCH = 0;
586 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
587 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
588 3 BLINK_LED();
589 3 break;
590 3 }
591 2 case VX_AF:
592 2 {
593 3 *EP0BUF = 0xAF; // return status of GPIFDONE bit
594 3 EP8BCH = 0x00; // Commit one zerolen IN pkt
595 3 EP8BCL = 0x00;
596 3 EP0BCH = 0;
597 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
598 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
599 3 BLINK_LED();
600 3 break;
601 3 }
602 2 case VX_B1:
603 2 { // examine flags...
604 3 *EP0BUF = EP8FIFOFLGS;
605 3 EP0BCH = 0;
606 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
607 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
608 3 BLINK_LED();
609 3 break;
610 3 }
611 2 case VX_B2:
612 2 { // examine flags...
613 3 *EP0BUF = EP2468STAT;
C51 COMPILER V6.10 GPIFBURST8A 06/27/2006 22:34:28 PAGE 11
614 3 EP0BCH = 0;
615 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
616 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
617 3 BLINK_LED();
618 3 break;
619 3 }
620 2 case VX_B3:
621 2 { // examine flags...
622 3 *EP0BUF = EP68FIFOFLGS;
623 3 EP0BCH = 0;
624 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
625 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
626 3 BLINK_LED();
627 3 break;
628 3 }
629 2 case VX_B4:
630 2 { // examine bc...
631 3 *EP0BUF = EP8BCH;
632 3 EP0BCH = 0;
633 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
634 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
635 3 BLINK_LED();
636 3 break;
637 3 }
638 2 case VX_B5:
639 2 { // examine bc...
640 3 *EP0BUF = EP8BCL;
641 3 EP0BCH = 0;
642 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
643 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
644 3 BLINK_LED();
645 3 break;
646 3 }
647 2 case VX_B6:
648 2 { // examine bc...
649 3 *EP0BUF = EP8FIFOBCH;
650 3 EP0BCH = 0;
651 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
652 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
653 3 BLINK_LED();
654 3 break;
655 3 }
656 2 case VX_B7:
657 2 { // examine bc...
658 3 *EP0BUF = EP8FIFOBCL;
659 3 EP0BCH = 0;
660 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
661 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
662 3 BLINK_LED();
663 3 break;
664 3 }
665 2 case VX_C1:
666 2 { // examine flags...
667 3 *EP0BUF = EP2FIFOFLGS;
668 3 EP0BCH = 0;
669 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
670 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
671 3 BLINK_LED();
672 3 break;
673 3 }
674 2 case VX_C2:
675 2 { // examine flags...
C51 COMPILER V6.10 GPIFBURST8A 06/27/2006 22:34:28 PAGE 12
676 3 *EP0BUF = EP2468STAT;
677 3 EP0BCH = 0;
678 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
679 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
680 3 BLINK_LED();
681 3 break;
682 3 }
683 2 case VX_C3:
684 2 { // examine flags...
685 3 *EP0BUF = EP24FIFOFLGS;
686 3 EP0BCH = 0;
687 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
688 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
689 3 BLINK_LED();
690 3 break;
691 3 }
692 2 case VX_C4:
693 2 { // examine bc...
694 3 *EP0BUF = EP2BCH;
695 3 EP0BCH = 0;
696 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
697 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
698 3 BLINK_LED();
699 3 break;
700 3 }
701 2 case VX_C5:
702 2 { // examine bc...
703 3 *EP0BUF = EP2BCL;
704 3 EP0BCH = 0;
705 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
706 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
707 3 BLINK_LED();
708 3 break;
709 3 }
710 2 case VX_C6:
711 2 { // examine bc...
712 3 *EP0BUF = EP2FIFOBCH;
713 3 EP0BCH = 0;
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