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File: fw.c Contents: Firmware frameworks task dispatcher and device request parser File: FX2.h Co

2005-09-23 Build the Skelecton of GoHT
    -09-25 Change the Power.sch
           Check all nodes and annotations
           Change the skelecton of GoHT,mainly for Premode.sch
           Depart the Premode.sch to two parts:Sample and SWIN

           Run ERC Check Rules,Found NO ERROR or WARNING
    -09-27 Add Memory.sch  QEP.sch

2005-09-30 Change Sample.sch and check it all

           Bill of Materials:

           Power.sch========   1-50
           Sample.sch=======   60-119
           DSP.sch==========   150-170
           Output.sch=======   200-209
           JTAG.sch=========   220-223
           USB.sch==========   250-258
           SwitchIn.sch=====   280-287
           Frequency.sch====   300-312
           QEP.sch==========   320-327
           MEM.sch==========   350-
2005-10-10 Change Power.sch  Delete A+5V A-5V replaced with LT1086
    -10-11 Set the PCB module...


2005-10-12 Add CPLD attatched to Frequency.sch for two detectors
           Build PCB.V.01
2005-11-09 Redraw PCB_1106.PCB
           DSP.sch delete ADCLOW (con. to AGND directly)
           ADCREFP->  AINB6
                      AINA1
           ADCREFM->  AINB7
                      AINA0
2005-11-16 Change Dsp.sch  Delete XRST Replaced with USBRST
           Change MEM.SCH  Change the sepuence of XDATA and XA Line of MEM
           Change Dsp.sch  Connect FLAGA,FLAGB,FLAGC,PKTEND,USBRST,WAKEUP With GPIOB0,1,2,3,4,5
           Change MEM.sch  Connect CE# With XZCS2
           Change USB.sch  Connect SLCS# With X\Z\C\S\0\A\N\D\1\
2005-11-21 Add Internal Planes
             Internal Plane 1:VDDA----Split Plane:A+15V VCORE
             Internal Plane 1:DGND----Split Plane:AGND
             Internal Plane 1:VDD ----Split Plane:A-15V
           Add Teardrops
           Add Polygons
2005-11-23 Check all SCHs and PCB

2005-11-28 Change Netlables for QEP and Sample,then reload nets to PCB

             QEP Channel A ====== QEP1
             QEP Channel B ====== QEP2
             QEP Channel Z ====== QEP3

2005-11-30 Delete Max4343 and redraw pcb

2005-12-02 Delete OP07s in QEP/Fre.sch
           Update PCB footprint of AD628s and AD620s
           Redraw PCB =====(Hard work!!!!!!!!!!!  :( )

2005-12-03 ||||||GoHT Ver.2.0 @HUST-HAE||||||||||

           Update footprint of USB_PORT
           Check all components and wires
           Add C1~C5 to Power nets including A+15v A-15v VDD VDDA VCORE
           Check all planes and redraw them...
2005-12-09 Check the PCB and SCHs
           Change Annotations of components
           Update SCHs by PCB.
           Replace silkscreen of designators for all components
           Add XRST# for PCB

2005-12-10 ||||||GoHT Ver.2.1 @HUST-HAE||||||||||

           Change the route mode:
           1:Rounded track
           2:45 Degreed track

           GoHT_Power.sch and GoHT_Power.pcb r build pm

2005-12-12
           GoHT_DSP.pcb enlarge the board size to fit the GoHT_Power.pcb's size

2005-12-13
           In USB.Sch Add SDA SCL!!
           Remove Dead Copper

2005-12-18 ||||||GoHT Ver.2.2 @HUST-HAE||||||||||
           Change the output.sch and pcb
           The swing of output frequency is +-10v
           Change the sample.sch and pcb!!!!

2005-12-20 Change the Footprint of POWER3 and POWER4 POWER2
           Change the RS806 of DBridge
           Redraw SCHs and PCBs

2006-01-05 Change the RESET KEY PCB Footprint
           Change the A3.3V Regulator 7805 to LT1085-3.3 LT1085-5.0




2006-03-28 ||||||GoHT Ver.3.0 @HUST-HAE||||||||||


GoHT Project
  |
  |
  |----GoHT_MB.PCB   [Main Board with DSP] Size:133.4-108.4(mm)
  |
  |----GoHT_ISO.PCB  [Isolation Board]
  |
  |----GoHT_PB.PCB   [Power Board]



2006.05-20
    Add UNL2803 in Output.Sch
    Add LM311 and attatchments in Frequency.sch
    Redraw GoHT_MB.DDB