gpminit.inc

本源码为BIOS研发技术剖析光盘原代码,是SIS530BIOS完整原代码.

;---------------------------------------------------------------;
;		        CLEAR_DEFAULT_SMRAM			;
;---------------------------------------------------------------;
;	Input : NONE						;
;		STACK PRESENT					;
;	Output: NONE						;
;	Register destroyed : (EAX),(DI)				;
;---------------------------------------------------------------;

clear_default_smram	proc	near

	push	cx				;
	push	es				;
	mov	cx,3000h			;
	mov	es,cx				; (es) = default SMRAM segment
	call	clear_smram			;
	pop	es				;
	pop	cx				;
	ret

clear_default_smram	endp

;---------------------------------------------------------------;
;			INIT_SMI_CPU_DATA			;
;---------------------------------------------------------------;
;	Input : (DS) SMI segment				;
;		(ES) SMI segment				;
;		(CS) SMI code source segment			;
;		(BL) bit 0 set for 32KB SMRAM			;
;		     bit 0 clear for 64KB or greater SMRAM	;
;		     bit 3  bit 2				;
;		       0      0   ... INTEL type SMI		;
;		       0      1   ... CYRIX type SMI		;
;		       1      0   ... AMD type SMI		;
;		       1      1   ... reserved			;
;		     bit 4 set for dual/multiple CPU present	;
;		     bit 4 clear for single CPU			;
;		     bit 5 set for IRQ based power management	;
;		     bit 5 clear for SMI based power management	;
;		     bit 6 set for SMI capable CPU		;
;		     bit 6 clear for non-SMI CPU		;
;		(BH) bit 3-0...no. of secondary CPU present	;
;		     bit 7-4...IRQ level for IRQ power management
;		(CH) cpu vendor #				;
;		(CL) cpu #					;
;		STACK PRESENT					;
;	Output: NONE						;
;	Register destroyed : (EAX),(EDX),(ESI),(EDI)		;
;---------------------------------------------------------------;

init_smi_cpu_data	proc	near

	mov	ds:misc_proc_smi_info,bl	;
	mov	ds:misc_proc_smi_info_cseg,bl	;

	movzx	ax,ch				; (ax) = cpu vendor#
	bts	ds:bios_detected_cpu_mfr,ax	; set proper bit for CPU vendor#
	bts	ds:bios_detected_cpu_mfr_cseg,ax;

	movzx	ax,cl				; (ax) = cpu#
	mov	ds:cpu_name_dseg,ax		; save cpu# 
	mov	ds:cpu_name_cseg,ax		;

	mov	al,bh				;
	and	al,00001111b			; (al) = # of secondary CPU present
	mov	ds:no_of_sec_cpu_present,al	;
	mov	ds:no_of_sec_cpu_present_cseg,al;

IF	IRQ_HANDLING_SUPPORT
	mov	al,bh				;
	shr	al,4				; (al) = IRQ level for IRQ based power management
	mov	ds:irq_used_for_pm,al		;
	mov	ds:irq_used_for_pm_cseg,al	;
ENDIF

	call	get_mapped_smi_seg_and_size	; CHIPSET HOOK HOOK HOOK...returns mapped smram segment info for different CPU and the size of SMRAM
	mov	ds:smi_code_seg_intel_amd_plus_cseg,ax; SMI mapped segment for INTEL/AMD PLUS CPU
						; shadow area used for IRQ based power management
	shr	eax,16				;
	mov	ds:smi_code_seg_cyrix_ti_cseg,ax; SMI mapped segment for CYRIX/TI CPU
	mov	ds:smi_code_seg_ibm_amd_non_plus_cseg,si; SMI mapped segment for IBM/AMD non-PLUS CPU
	mov	ds:smi_seg_size_cseg,edi	; SMI/IRQ segment size

	ret

init_smi_cpu_data	endp

;---------------------------------------------------------------;
;		        INIT_SMI_DATA				;
;---------------------------------------------------------------;
;	Input : (DS) SMI segment				;
;		(ES) SMI segment				;
;		(CS) SMI code source segment			;
;		(BL) bit 0 set for 32KB SMRAM			;
;		     bit 0 clear for 64KB or greater SMRAM	;
;		     bit 3  bit 2				;
;		       0      0   ... INTEL type SMI		;
;		       0      1   ... CYRIX type SMI		;
;		       1      0   ... AMD type SMI		;
;		       1      1   ... reserved			;
;		     bit 4 set for dual/multiple CPU present	;
;		     bit 4 clear for single CPU			;
;		     bit 5 set for IRQ based power management	;
;		     bit 5 clear for SMI based power management	;
;		     bit 6 set for SMI capable CPU		;
;		     bit 6 clear for non-SMI CPU		;
;		(BH) bit 3-0...no. of secondary CPU present	;
;		     bit 7-4...IRQ level for IRQ power management
;		(CH) cpu vendor #				;
;		(CL) cpu #					;
;		STACK PRESENT					;
;	Output: NONE						;
;	Register destroyed : (EAX),(EDX),(ESI),(EDI)		;
;---------------------------------------------------------------;

init_smi_data	proc	near

	push	cx				;

	call	setup_ide_data_area		; setup data area for IDE drives
	call	setup_disp_data_area		; setup data area for VESA VBE/PM
	mov	di,save_post_vga_vector		;
	call	save_int10_vectors		; save vectors for INT 10h execution

	push	ds				;
	push	int_vec_seg			;
	pop	ds				; (ds) = INT vector address segment
	mov	eax,ds:[10h*4]			; (eax) = INT 10H vecotr address
	mov	es:vga_bios_entry,eax		;
	mov	eax,ds:[16h*4]			; (eax) = INT 16H vector address
	mov	es:int_16_entry,eax		;

	push	bios_data_seg			;
	pop	ds				; (ds) = bios standard data segment (40H)
	test	machine_config,00000010b	; numeric co-processor present ?
	jz	short init_smi_data_01		; no...
	or	byte ptr es:misc_proc_info,npx_present; set for numeric co-processor present
	or	byte ptr es:misc_proc_info_cseg,npx_present; set for numeric co-processor present
init_smi_data_01:

	pop	ds				;

	pop	cx				;
	push	cx				;
	push	bx				;
	mov	di,chipset_config_area		;
	call	init_chipset_data		; CHIPSET HOOK HOOK HOOK...initialise chipset specific data area
	pop	bx				;

	pop	cx				;
	ret

init_smi_data	endp

;---------------------------------------------------------------;
;			SETUP_CPU_JMP_CODE			;
;---------------------------------------------------------------;
;	Input : (DS) SMRAM segment				;
;		(ES) SMRAM segment				;
;		(BL) bit 0 set for 32KB SMRAM			;
;		     bit 0 clear for 64KB or greater SMRAM	;
;		     bit 3  bit 2				;
;		       0      0   ... INTEL type SMI		;
;		       0      1   ... CYRIX type SMI		;
;		       1      0   ... AMD type SMI		;
;		       1      1   ... reserved			;
;		     bit 4 set for dual/multiple CPU present	;
;		     bit 4 clear for single CPU			;
;		     bit 5 set for IRQ based power management	;
;		     bit 5 clear for SMI based power management	;
;		     bit 6 set for SMI capable CPU		;
;		     bit 6 clear for non-SMI CPU		;
;		(BH) bit 3-0...no. of secondary CPU present	;
;		     bit 7-4...IRQ level for IRQ power management
;		STACK PRESENT					;
;	Output: NONE						;
;	Register destroyed : (AX),(DX),(DI)			;
;---------------------------------------------------------------;

setup_cpu_jmp_code	proc	near

	mov	di,8000h			;

IF	IRQ_HANDLING_SUPPORT
	test	bl,irq_power_management		; IRQ based power management ?
	jnz	short setup_cpu_jmp_10		; yes...
ENDIF

	mov	byte ptr [di],0e9h		; smi_seg:8000h ---> JMP 8019h
;;	mov	word ptr [di+01],0016h		; INTEL/AMD PLUS 32KB/64KB SMRAM
	mov	word ptr [di+01],(cgroup:intel_amd_plus_detect - cgroup:smi_code_begin -3)
						; INTEL/AMD PLUS 32KB/64KB SMRAM
	test	bl,smram_size_32kb		; 32KB SMRAM ?
	jnz	short setup_cpu_jmp_01		; yes...

	xor	di,di				;
	mov	byte ptr [di],0e9h		; smi_seg:0000h ---> JMP 801Fh
;;	mov	word ptr [di+01],801ch		; CYRIX/TI/IBM-CYRIX 64KB SMRAM
	mov	word ptr [di+01],(cgroup:crx_ti_detect - cgroup:smi_code_begin + orgbase - 3)
						; CYRIX/TI/IBM-CYRIX 64KB SMRAM

	mov	ax,ds:smi_code_seg_ibm_amd_non_plus_cseg; (ax) = smi code segment for IBM/AMD non-PLUS CPU
	mov	di,0fff0h			;
	mov	byte ptr [di],0eah		; smi_seg:fff0h ---> JMP smi_seg:801Ch
;;	mov	word ptr [di+01],801ch		; IBM/AMD non-PLUS/UMC 64KB SMRAM
	mov	word ptr [di+01],(cgroup:amd_non_plus_ibm_detect - cgroup:smi_code_begin + orgbase)
						; IBM/AMD non-PLUS/UMC 64KB SMRAM
	mov	word ptr [di+03],ax		;

	ret

setup_cpu_jmp_01:
	test	bl,smi_type_cyrix		; CYRIX type SMI ?
	jz	short setup_cpu_jmp_02		; no...INTEL type SMI

	mov	ax,ds:smi_code_seg_cyrix_ti_cseg; (ax) = smi code segment for CYRIX/TI CPU
	sub	ax,800h				; align in 64KB form
	mov	byte ptr [di],0eah		; smi_seg:0000h ---> JMP (smi_seg-800h):801Fh
;;	mov	word ptr [di+01],801fh		; CYRIX/TI 32KB SMRAM
	mov	word ptr [di+01],(cgroup:crx_ti_detect - cgroup:smi_code_begin + orgbase)
						; CYRIX/TI 32KB SMRAM
	mov	word ptr [di+03],ax		;

setup_cpu_jmp_02:
	ret

IF	IRQ_HANDLING_SUPPORT
setup_cpu_jmp_10:
	mov	word ptr [di],0aa55h		; put as ROM signature
	mov	byte ptr [di+02],40h		; set size as 32KB
	call	setup_irq_handler		; setup IRQ handler
	ret
ENDIF

setup_cpu_jmp_code	endp

;---------------------------------------------------------------;
;		HANDLE_SMBASE_RELOCATION			;
;---------------------------------------------------------------;
;	Input : (DS) SMRAM segment				;
;		(ES) SMRAM segment				;
;		(BL) bit 0 set for 32KB SMRAM			;
;		     bit 0 clear for 64KB or greater SMRAM	;
;		     bit 3  bit 2				;
;		       0      0   ... INTEL type SMI		;
;		       0      1   ... CYRIX type SMI		;
;		       1      0   ... AMD type SMI		;
;		       1      1   ... reserved			;
;		     bit 4 set for dual/multiple CPU present	;
;		     bit 4 clear for single CPU			;
;		     bit 5 set for IRQ based power management	;
;		     bit 5 clear for SMI based power management	;
;		     bit 6 set for SMI capable CPU		;
;		     bit 6 clear for non-SMI CPU		;
;		(BH) bit 3-0...no. of secondary CPU present	;
;		     bit 7-4...IRQ level for IRQ power management
;		(CH) cpu vendor #				;
;		(CL) cpu #					;
;		STACK PRESENT					;
;	Output: (CY) 00 ... SMBASE relocation not required	;
;			... SMBASE relocation required and code	;
;			    + data copied to default smbase area;
;			    successfully & (bl) bit 1 set as	;
;			    smbase relocation is required.	;
;		(CY) 01 ... SMBASE relocation is required but	;
;			    code + data could not be copied	;
;			    successfully.			;
;	Register destroyed : (BL),(SI),(DI)			;
;---------------------------------------------------------------;

handle_smbase_relocation	proc	near

	and	bl,not smbase_reloc_reqd	; clear bit 1 of (bl) for no smbase relocation
	test	bl,smi_type_mask or irq_power_management; INTEL type SMI/IRQ based power management ?
	jnz	short smbase_reloc_05		; no...does not require relocation
	test	bl,smram_size_32kb		; is it 32KB SMRAM ?
	jz	short smbase_reloc_06		; no...64KB or greater SMRAM
	cmp	word ptr ds:smi_code_seg_intel_amd_plus_cseg,3800h; does relocation needed ?
	jmp	short smbase_reloc_08		;

smbase_reloc_06:
	cmp	word ptr ds:smi_code_seg_intel_amd_plus_cseg,3000h; does relocation needed ?
smbase_reloc_08:
	jz	short smbase_reloc_05		; does not need relocation
smbase_reloc_07:
	or	bl,smbase_reloc_reqd		; (bl) bit 1 set for relocation needed
	call	copy_compare_default_smram	; copy SMRAM code+data to default SMRAM area
	ret

smbase_reloc_05:
	clc					; (cy) = 00 for no error
	ret

handle_smbase_relocation	endp

;---------------------------------------------------------------;
;*****************************************************************;
;*****************************************************************;
;**								**;
;**	(C)Copyright 1985-1996, American Megatrends Inc.	**;
;**								**;
;**			All Rights Reserved.			**;
;**								**;
;**		6145-F, Northbelt Parkway, Norcross,		**;
;**								**;
;**		Georgia - 30071, USA. Phone-(770)-246-8600.	**;
;**								**;
;*****************************************************************;
;*****************************************************************;
;---------------------------------------------------------------;
;		ROUTINES FOR SETTING UP IDE DATA AREA		;
;---------------------------------------------------------------;
;			SETUP_IDE_DATA_AREA			;
;---------------------------------------------------------------;
;	Input : (DS) PM BIOS data segment			;
;	Output: NONE						;
;	Register destroyed : NONE				;
;---------------------------------------------------------------;

setup_ide_data_area	proc	near

	pushad					;
;	db	09ah