moore.vhd

Moore型状态机设计,基于VHDL.能够根据微处理器的读写周期,分别对应存储器输出写使能WE和读使能OE信号.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY moore IS
PORT(clk,ready,read_write: IN Std_Logic;
     oe,we               : OUT Std_Logic);
END moore;

ARCHITECTURE state_machine OF Moore IS
TYPE state_type IS (idle,decision,read,write);
SIGNAL present_state,next_state: state_type;
BEGIN
   state_comb: PROCESS(present_state,ready,read_write)
   BEGIN
      CASE present_state IS
         WHEN idle => 
            oe<='0';
            we<='0';
            IF(ready='1') THEN 
               next_state<=decision;
            ELSE
               next_state<=idle;
            END IF;
         WHEN decision => 
            oe<='0';
            we<='0';
            IF(read_write='1') THEN 
               next_state<=read;
            ELSE
               next_state<=write;
            END IF;
         WHEN read => 
            oe<='1';
            we<='0';
            IF(ready='1') THEN 
               next_state<=idle;
            ELSE
               next_state<=read;
            END IF;
         WHEN write => 
            oe<='0';
            we<='1';
            IF(ready='1') THEN 
               next_state<=idle;
            ELSE
               next_state<=write;
            END IF;
      END CASE;
   END PROCESS state_comb;
   
   state_clocked:PROCESS(clk) 
   BEGIN
      IF(rising_edge(clk)) THEN
         present_state<=next_state;
      END IF;
   END PROCESS state_clocked;
END state_machine;