📄 regmap83xy.h.svn-base
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/********************************************************
THIS FILE CONTAINS ALL THE REGISTERS AND FIELDS MAPPING
********************************************************/
#ifndef _REGMAP83xy_H
#define _REGMAP83xy_H
/********************
REGISTERS DEFINITIONS
*********************/
enum Register_List
{
// HARDWARE REGISTERS
// Any question ? Contact Marc KODRNJA
// IC GENERAL CONTROL
R_CUT_ID =0, /*0x00*/
R_RESET,
R_TEST1,
R_TEST2,
R_I2S_CTRL,
R_STATUS,
R_I2S_SYNC_OFFSET,
// CLOCKING 1
R_SYS_CONFIG, /*0x07*/
R_FS1_DIV,
R_FS1_MD,
R_FS1_PE_H,
R_FS1_PE_L,
// DEMODULATOR
R_DEMOD_CTRL, /*0x0C*/
R_DEMOD_STAT,
R_AGC_CTRL,
R_AGC_GAIN,
R_DC_ERR_IF,
R_0x11,
// DEMODULATOR CH1
R_CARFQ1H, /*0x12*/
R_CARFQ1M,
R_CARFQ1L,
R_FIR1C0,
R_FIR1C1,
R_FIR1C2,
R_FIR1C3,
R_FIR1C4,
R_FIR1C5,
R_FIR1C6,
R_FIR1C7,
R_ACOEFF1,
R_BCOEFF1,
R_CRF1,
R_CETH1,
R_SQTH1,
R_CAROFFSET1,
R_GAIN,
R_SQTH1_MONO,
// DEMODULATOR CH2
R_IAGCR, /* 0x25*/
R_IAGCC,
R_IAGCS,
R_CARFQ2H,
R_CARFQ2M,
R_CARFQ2L,
R_FIR2C0,
R_FIR2C1,
R_FIR2C2,
R_FIR2C3,
R_FIR2C4,
R_FIR2C5,
R_FIR2C6,
R_FIR2C7,
R_ACOEFF2,
R_BCOEFF2,
R_SCOEFF,
R_SRF,
R_CRF2,
R_CETH2,
R_SQTH2,
R_CAROFFSET2,
R_SQTH2_GAIN,
R_ZWT_T_PLL_CTRL,
// NICAM
R_NICAM_CTRL, /*0x3D*/
R_NICAM_BER,
R_NICAM_STAT,
// STEREO FM
R_ZWT_CTRL, /*0x40*/
R_ZWT_TH,
R_ZWT_STAT,
// BTSC STEREO AND SAP
R_STEREO_CONF, /*0x43*/
R_STEREO_FSM_CONF,
R_STEREO_LEVEL_H,
R_STEREO_LEVEL_L,
R_SAP_CONF,
R_SAP_LEVEL_H,
R_SAP_LEVEL_L,
R_STE_CAR_LEVEL,
R_STE_PLL_STATUS,
R_STEREO_SAP_STATUS,
R_PLL_P_GAIN,
R_PLL_I_GAIN,
R_SAP_SQ_TH,
// EAI-J
R_EIAJ_CTRL0, /*0x50*/
R_EIAJ_CTRL1,
R_EIAJ_CTRL2,
// I2S MATRIX CONTROL
R_I2S_MATRIX_CTRL0, /*0x53*/
R_I2S_MATRIX_CTRL1,
R_I2S_MATRIX_CTRL2,
// ANALOG AND I2S OUT CONTROL
R_I2S_ADC_CTRL, /*0x56*/
R_SCART1_2_OUTPUT_CTRL,
R_SCART3_OUT_SCAUX_CTRL,
R_I2SO_DATA_CTRL,
// CLOCKING 2
R_FS2_DIV, /*0x5A*/
R_FS2_MD,
R_FS2_PE_H,
R_FS2_PE_L,
// I2S MATRIX INPUT CONTROL
R_I2S_MATRIX_INPUT_CTRL, /*0x5E*/
// ANTIFUSE STATUS
R_FUSE, /*0x5F*/
// NOT USED
R_0x60, /*0x60*/
R_0x61,
R_0x62,
R_0x63,
R_0x64,
R_0x65,
R_0x66,
R_0x67,
R_0x68,
R_0x69,
R_0x6A,
R_0x6B,
R_0x6C,
R_0x6D,
R_0x6E,
R_0x6F,
R_0x70,
R_0x71,
R_0x72,
R_0x73,
R_0x74,
R_0x75,
R_0x76,
R_0x77,
R_0x78,
R_0x79,
R_0x7A,
R_0x7B,
R_0x7C,
R_0x7D,
R_0x7E,
R_0x7F,
// DSP SOFTWARE REGISTERS
// Any question ? Contact Vianney TAUFOUR
// DSP HW CONTROL
R_DSP_HW_CONF, /*0x80*/
R_IRQ_STATUS,
// FW STATUS
R_STAT_DSP_INIT, /*0x82*/
R_STAT_FW_VERSION,
R_STAT_PATCH_VERSION,
R_STAT_ONCHIP_ALGOS,
// I2S INPUT CONFIGURATION
R_I2S_IN_CONF, /*0x86*/
R_I2S_IN_DELAY_CONF,
R_I2S_IN_SHIFT_RIGHT,
R_I2S_IN_MASK,
// OUTPUTS CONFIGURATION
R_HP_SCARTAUX_CONF, /*0x8A*/
R_SPDIF_CONF,
// DSP FW CONTROL
R_DSP_FW_CONF, /*0x8C*/
// AUTOSTANDARD CONFIGURATION
R_AMFM_MONO_STD_DET, /*0x8D*/
R_NICAMZWT_ST_STD_DET,
R_BTSCEIAJ_STD_DET,
R_AUTOSTD_CONF,
R_AUTOSTD_TIMES,
R_0x92,
// AUTOSTANDARD COEFFICIENTS CUSTOMIZATION
R_COEFF_VALID, /*0x93*/
R_COEFF_INDEX_MSB,
R_COEFF_INDEX_LSB,
R_COEFF_VALUE,
// DC REMOVAL MANUAL CONFIGURATION
R_DC_REMOVAL, /*0x97*/
// AM FM NICAM MANUAL CONFIGURATION
R_FMNICAM_BACKEND, /*0x98*/
// BTSC EIAJ MANUAL CONFIGURATION
R_BTSC_FINE_PRESCALE_ST, /*0x99*/
R_BTSC_FINE_PRESCALE_SAP,
R_BTSC_BACKEND,
R_0x9C,
// INPUT SIGNAL PRESCALING
R_PRESCALE_CONF, /*0x9D*/
R_PRESCALE_AM_EIAJ,
R_PRESCALE_FM_BTSC,
R_PRESCALE_NICAM,
R_PRESCALE_BTSC_ST,
R_PRESCALE_BTSC_SAP,
R_PRESCALE_EIAJ_ST,
R_PRESCALE_SCART,
R_PRESCALE_I2S0,
R_PRESCALE_I2S1,
R_PRESCALE_I2S2,
R_PRESCALE_I2S3,
// PEAK DETECTOR CONFIGURATION
R_PEAK_DETECTOR, /*0xA9*/
// DOWNMIX CONFIGURATION
R_DOWNMIX_CONF, /*0xAA*/
// LANGUAGE MATRIX CONFIGURATION
R_LANGUAGE_MATRIX, /*0xAB*/
// MAIN AUDIO MATRIX CONFIGURATION
R_AUDIO_MATRIX1, /*0xAC*/
R_AUDIO_MATRIX2,
R_AUDIO_MATRIX3,
R_AUDIO_MATRIX4,
// CHANNEL MATRIX CONFIGURATION
R_CHANNEL_MATRIX_LS, /*0xB0*/
R_CHANNEL_MATRIX_HP,
R_CHANNEL_MATRIX_SCART,
R_CHANNEL_MATRIX_SCARTAUX,
R_CHANNEL_MATRIX_SPDIF,
// LIP SYNC DELAY
R_AV_DELAY_CONF, /*0xB5*/
R_AV_DELAY_TIME_LS,
R_AV_DELAY_TIME_HP,
// DOLBY PROLOGIC II
R_PROLOGIC2_CONF1, /*0xB8*/
R_PROLOGIC2_CONF2,
R_PROLOGIC2_CONF3,
R_PROLOGIC2_LEVEL,
R_NOISE_GENERATOR,
R_SRND_DELAY,
// SRS TRUSURROUND XT
R_TRUSRND_CONF, /*0xBE*/
R_TRUSRND_DC_LEVEL,
R_TRUSRND_LEVEL,
R_TRUBASS_LS_CONF,
R_TRUBASS_LS_LEVEL,
R_TRUBASS_HP_CONF,
R_TRUBASS_HP_LEVEL,
// ST OMNISURROUND
R_OMNISRND_CONF1, /*0xC5*/
R_OMNISRND_CONF2,
R_OMNISRND_CONF3,
// ST BASS PROCESSING
R_DYNAMIC_BASS_LS, /*0xC8*/
R_DYNAMIC_BASS_HP,
R_BASS_ENHANCER_LS,
// SMART VOLUME CONFIGURATION
R_SVC_CONF, /*0xCB*/
R_SVC_LS_CONF,
R_SVC_LS_GAIN,
R_SVC_HP_CONF,
R_SVC_HP_GAIN,
// EQUALIZER
R_EQ_BT_CONF, /*0xD0*/
R_EQ_BT_LS_BAND1,
R_EQ_BT_LS_BAND2,
R_EQ_BT_LS_BAND3,
R_EQ_BT_LS_BAND4,
R_EQ_BT_LS_BAND5,
R_BT_HP_BASS,
R_BT_HP_TREBLE,
// LOUDNESS
R_LOUDNESS_LS, /*0xD8*/
R_LOUDNESS_HP,
// BEEPER
R_BEEPER_CONF1, /*0xDA*/
R_BEEPER_CONF2,
R_BEEPER_CONF3,
R_BEEPER_CONF4,
// SUBWOOFER CHANNEL MANAGEMENT
R_BASS_MNGT_CONF1, /*0xDE*/
R_BASS_MNGT_CONF2,
// VOLUME
R_ANTICLIPPING, /*0xE0*/
R_VOLUME_MODES,
R_MUTE_DIGITAL,
R_MUTE_DAC,
R_VOLUME_LS_L_COARSE,
R_VOLUME_LS_L_FINE,
R_VOLUME_LS_R_COARSE,
R_VOLUME_LS_R_FINE,
R_VOLUME_LS_C,
R_VOLUME_LS_SUB,
R_VOLUME_LS_SL,
R_VOLUME_LS_SR,
R_VOLUME_HP_L_COARSE,
R_VOLUME_HP_L_FINE,
R_VOLUME_HP_R_COARSE,
R_VOLUME_HP_R_FINE,
R_VOLUME_SCART,
R_VOLUME_SCARTAUX,
// PARAMETRIC EQUALIZER
R_PARAM_EQ_CONF1, /*0xF2*/
R_PARAM_EQ_CONF2,
R_PARAM_EQ_CONF3,
// DEBUG REGISTERS
R_0xF5, /*0xF5*/
R_0xF6,
R_DEBUG_INPUT_DISABLE,
R_DEBUG_AUTOSTD,
R_STAT_DC_REMOVAL_L,
R_STAT_DC_REMOVAL_R,
// DSP STATUS
R_STAT_STD_HP_I2S_IN, /*0xFB*/
R_STAT_AUTOSTD,
R_STAT_PEAK_L,
R_STAT_PEAK_R,
R_STAT_PEAK_L_R,
/* Number of Registers */
NBREG
};
/********************************************
FIELDS DEFINITIONS
from most (MSB) to less (LSB) significant bit
*********************************************/
enum Field_List
{
// HARDWARE FIELDS
// Any question ? Contact Marc KODRNJA
// IC GENERAL CONTROL
// R_CUT_ID /*0x00*/
F_SCAN_MODE,
F_CUT_NUMBER,
F_CHIP_VERSION,
// R_RESET
F_BUS_EXP,
F_RESET_6,
F_RESET_5,
F_EN_STBY,
F_CLOCK_DOWN,
F_SOFT_LRST2,
F_SOFT_LRST1,
F_SOFT_RST,
// R_TEST1
F_TEST1_7,
F_TEST1_6,
F_TEST1_5,
F_TST_SM_DIS,
F_TST_AUTO,
F_TST_IF,
// R_TEST2
F_TST_MODE,
// R_I2S_CTRL
F_I2S_CTRL_7,
F_SYNC_SIGN,
F_I2S_SRC_FORCE,
F_LOCK_TH,
F_LOCK_MODE,
F_SYNC_CST,
// R_STATUS
F_PATCH_FLAG,
F_I2S_STAT_6,
F_I2S_STAT_5,
F_I2S_STAT_4,
F_I2S_STAT_3,
F_I2S_STAT_2,
F_LR_OFF,
F_LOCK_FLAG,
// R_I2S_SYNC_OFFSET
F_I2S_SFO,
// CLOCKING 1
// R_SYS_CONFIG /*0x07*/
F_SYNC_PLL,
F_OPEN_PLL,
F_INPUT_FREQ,
F_SYS_CONFIG_1,
F_I2S_SYNC_RGE,
// R_FS1_DIV
F_EN_PROG,
F_FS1_DIV_6,
F_NDIV1,
F_FS1_DIV_3,
F_SDIV1,
// R_FS1_MD
F_FS1_MD_7,
F_FS1_MD_6,
F_FS1_MD_5,
F_MD1,
// R_FS1_PE_H
F_PE_H1,
// R_FS1_PE_L
F_PE_L1,
// DEMODULATOR
// R_DEMOD_CTRL /*0x0C*/
F_DEMOD_CTRL_7,
F_DEMOD_CTRL_6,
F_NIC_FLT_MODE,
F_DAGC_BYPASS,
F_AM_SEL,
F_DEMOD_MODE,
// R_DEMOD_STAT
F_DEMOD_STAT_7,
F_DEMOD_STAT_6,
F_FM1_SQ_MONO,
F_QPSK_LK,
F_FM2_CAR,
F_FM2_SQ,
F_FM1_CAR,
F_FM1_SQ,
// R_AGC_CTRL
F_AGC_CMD,
F_AGC_CTRL_6,
F_IF_SELECT,
F_AGC_REF,
F_AGC_CST,
// R_AGC_GAIN
F_AGC_GAIN_7,
F_AGC_ERR,
F_SIG_OVER,
F_SIG_UNDER,
// R_DC_ERR_IF
F_DC_ERR,
// R_0x11
F_0x11,
// DEMODULATOR CH1
// R_CARFQ1H /*0x12*/
F_CARFQ1H,
// R_CARFQ1M
F_CARFQ1M,
// R_CARFQ1L
F_CARFQ1L,
// R_FIR1C0
F_FIR1C0,
// R_FIR1C1
F_FIR1C1,
// R_FIR1C2
F_FIR1C2,
// R_FIR1C3
F_FIR1C3,
// R_FIR1C4
F_FIR1C4,
// R_FIR1C5
F_FIR1C5,
// R_FIR1C6
F_FIR1C6,
// R_FIR1C7
F_FIR1C7,
// R_ACOEFF1
F_ACOEFF1,
// R_BCOEFF1
F_BCOEFF1,
// R_CRF1
F_CRF1,
// R_CETH1
F_CETH1,
// R_SQTH1
F_SQTH1,
// R_CAROFFSET1
F_CAROFFSET1,
// R_GAIN
F_CHANNEL_GAIN_7,
F_SQTH_GAIN,
F_SQ_WIDE,
F_SQ_SELECT,
F_CH_GAIN,
// R_SQTH1_MONO
F_SQTH1_MONO,
// DEMODULATOR CH2
// R_IAGCR /* 0x25*/
F_IAGC_REF,
// R_IAGCC
F_IAGC_OFF,
F_NIC_FLT_EN,
F_MONO_FLT_EN,
F_BG_FLT_EN,
F_MONO_PROG,
F_IAGC_CST,
// R_IAGCS
F_IAGC_CTRL,
// R_CARFQ2H
F_CARFQ2H,
// R_CARFQ2M
F_CARFQ2M,
// R_CARFQ2L
F_CARFQ2L,
// R_FIR2C0
F_FIR2C0,
// R_FIR2C1
F_FIR2C1,
// R_FIR2C2
F_FIR2C2,
// R_FIR2C3
F_FIR2C3,
// R_FIR2C4
F_FIR2C4,
// R_FIR2C5
F_FIR2C5,
// R_FIR2C6
F_FIR2C6,
// R_FIR2C7
F_FIR2C7,
// R_ACOEFF2
F_ACOEFF2,
// R_BCOEFF2
F_BCOEFF2,
// R_SCOEFF
F_SCOEFF,
// R_SRF
F_SRF,
// R_CRF2
F_CRF2,
// R_CETH2
F_CETH2,
// R_SQTH2
F_SQTH2,
// R_CAROFFSET2
F_CAROFFSET2,
// R_SQTH2_GAIN
F_SQTH2_GAIN_7,
F_SQTH2_GAIN_6,
F_SQTH2_GAIN_5,
F_SQTH2_GAIN_4,
F_SQTH2_GAIN_3,
F_SQTH2_GAIN,
// ZWT_T_PLL_CTRL
F_KB_PILOT,
F_KAK0_PILOT,
F_ZWT_T_PLL_CTRL_3,
F_KB_TONE,
F_KAK0_TONE,
// NICAM
// R_NICAM_CTRL /*0x3D*/
F_DIF_POL,
F_ECT,
F_NICAM_CTRL_5,
F_NICAM_CTRL_4,
F_NICAM_CTRL_3,
F_MAE,
// R_NICAM_BER
F_ERROR,
// R_NICAM_STAT
F_NIC_DET,
F_F_MUTE,
F_LOA,
F_CBI,
F_NIC_MUTE,
// STEREO FM
// R_ZWT_CTRL /*0x40*/
F_LRST_TONE_OFF,
F_STD_MODE,
F_ZWT_CTRL_5,
F_ZWT_TIME,
F_TSCTRL,
// R_ZWT_TH
F_THRESH_PILOT,
F_THRESH_TONE,
// R_ZWT_STAT
F_LRST_TONE_OFF_,
F_ZWT_STAT_6,
F_ZWT_STAT_5,
F_ZWT_STAT_4,
F_ZW_STAT_RDY,
F_ZW_DET,
F_ZW_ST,
F_ZW_DM,
// BTSC STEREO AND SAP
// R_STEREO_CONF /*0x43*/
F_LOCK_TH_STE,
F_LOOP_GAIN,
F_FREQ_PIL,
F_RESET,
// R_STEREO_FSM_CONF
F_STEREO_FSM_CONF_7,
F_STEREO_FSM_CONF_6,
F_BYPASS,
F_FSM_OFF,
F_GAIN_INI,
F_STE_DEM,
// R_STEREO_LEVEL_H
F_STE_LEV_H,
// R_STEREO_LEVEL_L
F_STE_LEV_L,
// R_SAP_CONF
F_SAP_CONF_7,
F_SAP_CONF_6,
F_SAP_CONF_5,
F_SAP_CONF_4,
F_SAP_CONF_3,
F_SAP_CONF_2,
F_SAP_CONF_1,
F_SAP_SEL,
// R_SAP_LEVEL_H
F_SAP_LEV_H,
// R_SAP_LEVEL_L
F_SAP_LEV_L,
// R_STE_CAR_LEVEL
F_STE_CAR_LEV,
// R_STE_PLL_STATUS
F_STE_PLL_STATUS_7,
F_STE_PLL_STATUS_6,
F_PLL_LOOP_GAIN,
F_PLL_OVER,
F_PLL_LOCK_DET,
F_PLL_STE_DET,
// R_STEREO_SAP_STATUS
F_STEREO_SAP_STATUS_7,
F_OVER,
F_LOCK_DET,
F_STE_DET,
F_STEREO_SAP_STATUS_3,
F_STEREO_SAP_STATUS_2,
F_SQ_DET,
F_SAP_DET,
// R_PLL_P_GAIN
F_PLL_P_GAIN,
// R_PLL_I_GAIN
F_PLL_I_GAIN_7,
F_PLL_I_GAIN_6,
F_PLL_I_GAIN_5,
F_PLL_I_GAIN_4,
F_PLL_I_GAIN,
// R_SAP_SQ_TH
F_SAP_SQ_TH,
// EAI-J
// R_EIAJ_CTRL0 /*0x50*/
F_EIAJ_CTRL0,
// R_EIAJ_CTRL1
F_EIAJ_CTRL1,
// R_EIAJ_CTRL2
F_EIAJ_CTRL2,
// I2S MATRIX CONTROL
// R_I2S_MATRIX_CTRL0 /*0x53*/
F_I2S_DATA1_DIR,
F_I2S_DATA1_CTRL,
F_I2S_DATA0_DIR,
F_I2S_DATA0_CTRL,
// R_I2S_MATRIX_CTRL1
F_I2S_DATA3_DIR,
F_I2S_DATA3_CTRL,
F_I2S_DATA2_DIR,
F_I2S_DATA2_CTRL,
// R_I2S_MATRIX_CTRL2
F_I2S_IN_SEL_P,
F_I2S_P80_P100,
F_OUTPUT_SLAVE,
F_I2S_CLK_DIR,
F_I2SA_DATA_DIR,
F_I2SA_DATA_CTRL,
// ANALOG AND I2S OUT CONTROL
// R_I2S_ADC_CTRL /*0x56*/
F_DAC_PWR_UP,
F_ADC_POWER_UP,
F_ADC_INPUT_SEL,
// R_SCART1_2_OUTPUT_CTRL
F_SC2_MUTE,
F_SC2_OUTPUT_SEL,
F_SC1_MUTE,
F_SC1_OUTPUT_SEL,
// R_SCART3_OUT_SCAUX_CTRL
F_SCART3_OUTPUT_CTRL_7,
F_SCAUX_SEL,
F_SC3_MUTE,
F_SC3_OUTPUT_SEL,
// R_I2SO_DATA_CTRL
F_I2SO_DATA_CTRL_7,
F_I2SO_DATA1_CTRL,
F_I2SO_DATA_CTRL_3,
F_I2SO_DATA0_CTRL,
// CLOCKING 2
// R_FS2_DIV /*0x5A*/
F_FS2_DIV_7,
F_NDIV2,
F_FS2_DIV_3,
F_SDIV2,
// R_FS2_MD
F_FS2_MD_7,
F_FS2_MD_6,
F_FS2_MD_5,
F_MD2,
// R_FS2_PE_H
F_PE_H2,
// R_FS2_PE_L
F_PE_L2,
// I2S MATRIX INPUT CONTROL
// R_I2S_MATRIX_INPUT_CTRL /*0x5E*/
F_I2S_IN_SEL_S,
F_I2S_IN_SEL_LR,
F_I2S_IN_SEL_0,
F_I2S_IN_SEL_1,
// ANTIFUSE STATUS
// R_FUSE /*0x5F*/
F_FUSE,
// NOT USED
// R_0x60 /*0x60*/
F_0x60,
// R_0x61
F_0x61,
// R_0x62
F_0x62,
// R_0x63
F_0x63,
// R_0x64
F_0x64,
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