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📄 ioctrl.h.svn-base

📁 最新火热的CX32 源代码
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/*******************************************************************************
 *
 * File: IOCtrl.h
 *
 * Purpose: This file declare functions about IO control
 *
 * Author: JimNie
 *
 * Copyright (C) 2004, Trident Multimedia Technologies (Shanghai) Co., Ltd.
 *
 ***************************************************************************/
#ifndef _IOCTRL_H_
#define _IOCTRL_H_

#include "tvconfig.h"

/*******************************************************************
    define io for LCD203A board(LCD) here
*******************************************************************/
#ifdef _CX32_LCD203_ENABLE_
#ifdef USE_T_QUAD
    #define INT_PRIORITY_A                  0x05
    #define INT_PRIORITY_B                  0x04
    #define INT_PRIORITY_C                  0x03
    #define INT_PRIORITY_D                  0x02
    #define INT_PRIORITY_E                  0x01
#else
    #define INT_PRIORITY_A                  0x06
    #define INT_PRIORITY_B                  0x05
    #define INT_PRIORITY_C                  0x04
    #define INT_PRIORITY_D                  0x03
    #define INT_PRIORITY_E                  0x02
#endif
    #define INT_PRIORITY_F                  0x01
    #define INT_PRIORITY_G                  0x01
    #define INT_PRIORITY_OFF                0x00

    /*
    //Timer A2 downcount
    #define REMOTE_TIME_MAX                 20000
    #define REMOTE_TIMER_STOP               TA23RUN &= 0xF0 //ta2s = 0
    #define REMOTE_TIMER_START              TA23RUN |= 0x08 //ta2s = 1
    #define REMOTE_TIMER_CLEAR              TA2REG = (Byte)REMOTE_TIME_MAX,TA3REG = REMOTE_TIME_MAX>>8
    #define REMOTE_TIMER_CLEAR_PEND
    #define REMOTE_TIMER_LOAD
    #define REMOTE_TIMER_VALUE              //((REMOTE_TIME_MAX - ta2) / 70)
    
    //Timer A3 upcount
    #define SIGNAL_COUNTER_STOP             TA45RUN &= 0xF0 //ta3s = 0
    #define SIGNAL_COUNTER_START            TA45RUN |= 0x08 //ta3s = 1
    #define SIGNAL_COUNTER_CLEAR            TA4REG = 0, TA5REG = 0 //ta3 = 0
    #define SIGNAL_COUNTER_LOAD
    #define SIGNAL_COUNTER_VALUE            //ta3
    */

//---------------------------------------------------------------------
    #define TimerEnterCriticalSection()     INTTA0 = INT_PRIORITY_OFF,INTTA1 = INT_PRIORITY_OFF //ta0ic = INT_PRIORITY_OFF
    #define TimerLeaveCriticalSection()     INTTA0 = INT_PRIORITY_A,INTTA1 = INT_PRIORITY_A //ta0ic = INT_PRIORITY_A
    
    #ifdef _NEW_TIMER_ASSIGN_
    #define CMD_IN_CRITICAL                 //tb1ic = INT_PRIORITY_OFF
    #define CMD_OUT_CRITICAL                //tb1ic = INT_PRIORITY_B
    #else
    #define CMD_IN_CRITICAL                 INTTB00 = INT_PRIORITY_OFF //ta1ic = INT_PRIORITY_OFF
    #define CMD_OUT_CRITICAL                INTTB00 = INT_PRIORITY_B //ta1ic = INT_PRIORITY_B
    #endif
    
    #define HI2C_IO_MODE                    g_p6fc_buf&=0xF9;P6FC=g_p6fc_buf
                                            //P62F = 0, P61F = 0
    #define HI2C_I2C_MODE                   g_p6fc_buf|=0x06;P6FC=g_p6fc_buf
                                            //P62F = 1, P61F = 1
    #define HI2C_SCL_INMODE                 g_p6cr_buf&=0xFB;P6CR=g_p6cr_buf
                                            //P62C = 0
    #define HI2C_SCL_OUTMODE                g_p6cr_buf|=0x04;P6CR=g_p6cr_buf
                                            //P62C = 1
    #define HI2C_SDA_INMODE                 g_p6cr_buf&=0xFD;P6CR=g_p6cr_buf
                                            //P61C = 0
    #define HI2C_SDA_OUTMODE                g_p6cr_buf|=0x02;P6CR=g_p6cr_buf
                                            //P61C = 1
    #define HI2C_ALL_INMODE                 HI2C_SCL_INMODE;HI2C_SDA_INMODE
                                            //P62C = 0, P61C = 0
    #define HI2C_ALL_OUTMODE                HI2C_SCL_OUTMODE;HI2C_SDA_OUTMODE
                                            //P62C = 1, P61C = 1
    #define HI2C_SCL_SET                    g_p6_buf=P6;g_p6_buf|=0x04;P6=g_p6_buf
                                            //P62 = 1
    #define HI2C_SCL_CLR                    g_p6_buf=P6;g_p6_buf&=0xFB;P6=g_p6_buf
                                            //P62 = 0
    #define HI2C_SDA_SET                    g_p6_buf=P6;g_p6_buf|=0x02;P6=g_p6_buf
                                            //P61 = 1
    #define HI2C_SDA_CLR                    g_p6_buf=P6;g_p6_buf&=0xFD;P6=g_p6_buf
    
    #define GAL_DISABLE
    #define GAL_ENABLE
    
    #define SI2C_SCL_SET                    g_p7_buf=P7;g_p7_buf|=0x02;P7=g_p7_buf
                                            //P71 = 1
    #define SI2C_SCL_CLR                    g_p7_buf=P7;g_p7_buf&=0xFD;P7=g_p7_buf
                                            //P71 = 0
    #define SI2C_SCL_GET                    g_p7_buf=P7
                                         
    #define SI2C_SCL_STATUS                 (Bool)(g_p7_buf&0x02)

    #define SI2C_SCL_ISTRUE                 //P71 == 1
    
    #define SI2C_SCL_ISFALSE                //P71 == 0
    
    #define SI2C_SDA_SET                    g_p7_buf=P7;g_p7_buf|=0x01;P7=g_p7_buf
                                            //P70 = 1
    #define SI2C_SDA_CLR                    g_p7_buf=P7;g_p7_buf&=0xFE;P7=g_p7_buf
                                            //P70 = 0
    #define SI2C_SDA_GET                    g_p7_buf=P7

    #define SI2C_SDA_STATUS                 (Bool)(g_p7_buf&0x01)
    
    #define SI2C_SDA_ISTRUE                 //P70 == 1
    
    #define SI2C_SDA_ISFALSE                //P70 == 0
    
    #define SI2C_SCL_INMODE                 g_p7cr_buf&=0xFD;P7CR=g_p7cr_buf
                                            //P71C = 0
    #define SI2C_SCL_OUTMODE                g_p7cr_buf|=0x02;P7CR=g_p7cr_buf
                                            //P71C = 1
    #define SI2C_SDA_OUTMODE                g_p7cr_buf|=0x01;P7CR=g_p7cr_buf
                                            //P70C = 1
    #define SI2C_SDA_INMODE                 g_p7cr_buf&=0xFE;P7CR=g_p7cr_buf
                                            //P70C = 0
    #define SI2C_ALL_OUTMODE                SI2C_SCL_OUTMODE;SI2C_SCL_OUTMODE
    
    #define SI2C_ALL_INMODE                 SI2C_SCL_INMODE;SI2C_SDA_INMODE
    
    #define E2PROM_PIN_PROTECTON            g_p7_buf=P7;g_p7_buf|=0x04;P7=g_p7_buf
                                            //P72 = 1
    #define E2PROM_PIN_PROTECTOFF           g_p7_buf=P7;g_p7_buf&=0xFB;P7=g_p7_buf
                                        //P72 = 0

    #define CLEAR_WATCHDOG
    
    #define UART_CTSHOLD                    P95 = 1   // g_p9_buf=P9;g_p9_buf|=0x20;P9=g_p9_buf
                                           
    #define UART_CTSRELEASE                 P95 = 0    //g_p9_buf=P9;g_p9_buf&=0xDF;P9=g_p9_buf
                                            //P95 = 0 
    #define UART_ENABLE_RINT                INTRX1 = INT_PRIORITY_F //UART1 interrupt set
    #define UART_DISABLE_RINT               INTRX1 = INT_PRIORITY_OFF //Disable
    #define UART_ENABLE_TINT                INTTX1 = INT_PRIORITY_E //UART1 interrupt set
    #define UART_DISABLE_TINT               INTTX1 = INT_PRIORITY_OFF //Disable
    
    #define UART_ENABLE_RECEIVE             UART_ENABLE_RINT, UART_CTSRELEASE, Uart1PutByte(XON)
    #define UART_DISABLE_RECEIVE            UART_CTSHOLD, UART_DISABLE_RINT
    
    //-------------------------------------------------------------------
    #define POWER_PROTECT_TRUE             // (ad7 < 0x40) 
    #define BUSOFF_PIN_IS_TRUE             // (ad6 < 0x80)
    
    
    #define YPBPR1_PIN_ISTRUE          //(g_p9_buf&0x10)== 0x10//  p9_4 == 1
    #define YPBPR1_PIN_ISFALSE         //(g_p9_buf|0xEF)== 0xEF// p9_4 == 0
    #define DGAUSE_PIN_SET            //g_p9_buf=P9;g_p9_buf|=0x08;P9=g_p9_buf// p9_3 = 1
    #define DGAUSE_PIN_CLR            //g_p9_buf=P9;g_p9_buf&=0xF7;P9=g_p9_buf// p9_3 = 0
    #define SVIDEO1_PIN_ISTRUE        //(g_p9_buf|0xFB) == 0xFB // p9_2 == 0//1
    #define SVIDEO1_PIN_ISFALSE       //(g_p9_buf&0x04)== 0x04 // p9_2 == 1//0


    #if 0
    #define AUDIOSWITCH_PIN1_SET            //g_p7_buf=P7;g_p7_buf|=0x40;P7=g_p7_buf//p7_6 = 1
    #define AUDIOSWITCH_PIN1_CLR            //g_p7_buf=P7;g_p7_buf&=0xBF;P7=g_p7_buf//p7_6 = 0
    #define AUDIOSWITCH_PIN0_SET        //  g_p7_buf=P7;g_p7_buf|=0x20;P7=g_p7_buf//p7_5 = 1
    #define AUDIOSWITCH_PIN0_CLR    //      g_p7_buf=P7;g_p7_buf&=0xDF;P7=g_p7_buf//p7_5 = 0
    #endif
    
    #define ISP_PIN_IS_TRUE         //  g_p6_buf=P6;g_p6_buf|=0x20;P6=g_p6_buf          //  p6_5 == 1
    #define ISP_PIN_IS_FALSE          //g_p6_buf=P6;g_p6_buf&=0xDF;P6=g_p6_buf      //p6_5 == 0
    #define MONITOR_PIN_SET          // g_p6_buf=P6;g_p6_buf|=0x10;P6=g_p6_buf      //p6_4 = 1
    #define MONITOR_PIN_CLR        //   g_p6_buf=P6;g_p6_buf&=0xEF;P6=g_p6_buf      //p6_4 = 0
    #define DVRESET_PIN_SET           P97 = 1   //g_p9_buf=P9;g_p9_buf|=0x80;P9=g_p9_buf      //p9_7 = 1
    #define DVRESET_PIN_CLR           P97= 0    //g_p9_buf=P9;g_p9_buf&=0x7F;P9=g_p9_buf      //p9_7 = 0
    #define RESET_L_PIN_SET           P96 = 1   //g_p9_buf=P9;g_p9_buf|=0x40;P9=g_p9_buf    //p9_6 = 1
    #define RESET_L_PIN_CLR           P96 = 0   //g_p9_buf=P9;g_p9_buf&=0xBF;P9=g_p9_buf    //p9_6 = 0
    #define FLASH_PIN_SET          //   g_p6_buf=P6;g_p6_buf|=0x01;P6=g_p6_buf      //p6_0 = 1
    #define FLASH_PIN_CLR          //   g_p6_buf=P6;g_p6_buf&=0xFE;P6=g_p6_buf      //p6_0 = 0
    
#if 1 //--------YYM_06_04_15 for[]
    #define POWER_ON                  g_p4_buf=P4;g_p4_buf|=0x02;P4=g_p4_buf      //p4_1 = 1
    #define POWER_OFF                 g_p4_buf=P4;g_p4_buf&=0xFD;P4=g_p4_buf      //p4_1 = 0
#else
    #define POWER_OFF                  g_p4_buf=P4;g_p4_buf|=0x02;P4=g_p4_buf      //p4_1 = 1
    #define POWER_ON                 g_p4_buf=P4;g_p4_buf&=0xFD;P4=g_p4_buf      //p4_1 = 0
#endif
    #define MUTE_PIN_ENABLE       	P92 = 0//    g_p1_buf=P1;g_p1_buf&=0xDF;P1=g_p1_buf      //p1_5 = 0
    #define MUTE_PIN_DISABLE     	P92 = 1//     g_p1_buf=P1;g_p1_buf|=0x20;P1=g_p1_buf      //p1_5 = 1
    #define PALN_PIN_SET          //    g_p1_buf=P1;g_p1_buf|=0x10;P1=g_p1_buf      //p1_4 = 1
    #define PALN_PIN_CLR                    //      g_p1_buf=P1;g_p1_buf&=0xEF;P1=g_p1_buf          //p1_4 = 0
    #define ABL_SW_SET                  //          g_p1_buf=P1;g_p1_buf|=0x08;P1=g_p1_buf          //p1_3 = 1
    #define ABL_SW_CLR                      //      g_p1_buf=P1;g_p1_buf&=0xF7;P1=g_p1_buf          //p1_3 = 0
    //#define VIDEOSWITCH_PIN1_SET  //    g_p1_buf=P1;g_p1_buf|=0x04;P1=g_p1_buf      //p1_2 = 1
    //#define VIDEOSWITCH_PIN1_CLR //     g_p1_buf=P1;g_p1_buf&=0xFB;P1=g_p1_buf      //p1_2 = 0
    //#define VIDEOSWITCH_PIN0_SET   //   g_p1_buf=P1;g_p1_buf|=0x02;P1=g_p1_buf      //p1_1 = 1
    //#define VIDEOSWITCH_PIN0_CLR  //    g_p1_buf=P1;g_p1_buf&=0xFD;P1=g_p1_buf      //p1_1 = 0
    //#define LED_R_PIN_SET               g_p8_buf=P8;g_p8_buf|=0x04;P8=g_p8_buf      //p1_0 = 1
    //#define LED_R_PIN_CLR               g_p8_buf=P8;g_p8_buf&=0xFB;P8=g_p8_buf      //p1_0 = 0
    //#define LED_G_PIN_SET               g_p8_buf=P8;g_p8_buf|=0x08;P8=g_p8_buf      //p1_0 = 1
    //#define LED_G_PIN_CLR               g_p8_buf=P8;g_p8_buf&=0xF7;P8=g_p8_buf      //p1_0 = 0
    #define LED_PIN_SET                 g_p6_buf=P6;g_p6_buf|=0x01;P6=g_p6_buf      //p1_0 = 1
    #define LED_PIN_CLR                 g_p6_buf=P6;g_p6_buf&=0xFE;P6=g_p6_buf      //p1_0 = 0

    #define REMOTE_TIMER_STOP               TB0RUN = 0x0C //0x0c
    #define REMOTE_TIMER_START              TB0RUN = 0x0D //0x0d
    #define REMOTE_TIMER_CLEAR              {TB0RUN = 0x0C; TB0RUN = 0x0D;}
    #define REMOTE_TIMER_LOAD               TB0MOD &= 0xDF            
    #define REMOTE_TIMER_CONDITION     TB0MOD |= 0x20            
    #define REMOTE_TIMER_VALUE              TB0CP0  

    //#define AUDIO_SW1_SET               P24 = 1 //g_p2_buf=P2;g_p2_buf|=0x10;P2=g_p2_buf      //p2_4 = 1
    //#define AUDIO_SW1_CLR               P24 = 0 //g_p2_buf=P2;g_p2_buf&=0xEF;P2=g_p2_buf      //p2_4 = 0
    //#define AUDIO_SW2_SET              P25 = 1// g_p2_buf=P2;g_p2_buf|=0x08;P2=g_p2_buf      //p2_3 = 1
    //#define AUDIO_SW2_CLR              P25 = 0//g_p2_buf=P2;g_p2_buf&=0xF7;P2=g_p2_buf      //p2_3 = 0

// ++cl 061027 for 2hdmi&3scart begin
    #define AUDIO_LR_SW1_SET        P24 = 1
    #define AUDIO_LR_SW1_CLR        P24 = 0
    #define AUDIO_LR_SW2_SET        P25 = 1
    #define AUDIO_LR_SW2_CLR        P25 = 0
#ifdef _2Hdmi_3Scart_
    #define VIDEO_SW3_SET              P90 = 1
    #define VIDEO_SW3_CLR              P90 = 0
    #define VIDEO_SW4_SET              P60 = 1
    #define VIDEO_SW4_CLR              P60 = 0
    #define YUV_SW4_SET                  P91 = 1
    #define YUV_SW4_CLR                  P91 = 0
#endif
// ++cl 061027 for 2hdmi&3scart end
    #define LVDS_PWR_ON                 P73 = 1    //g_p9_buf=P9;g_p9_buf|=0x01;P9=g_p9_buf      //p9_0 = 1
    #define LVDS_PWR_OFF                P73 = 0     //g_p9_buf=P9;g_p9_buf&=0xFE;P9=g_p9_buf      //p9_0 = 0

    #define BKLT_CNTL_ON                    g_p7_buf=P7;g_p7_buf|=0x10;P7=g_p7_buf      //p7_4 = 1
    #define BKLT_CNTL_OFF                   g_p7_buf=P7;g_p7_buf&=0xEF;P7=g_p7_buf      //p7_4 = 0
#if 1 //--------YYM_06_07_27 for[]
    #define HDMI_HOTPLUG_OUTMODE		g_p8cr_buf|=0x08;P8CR=g_p8cr_buf
    #define HDMI_HOTPLUG_INMODE			g_p8cr_buf&=0xF7;P8CR=g_p8cr_buf
    #define HDMI_HOTPLUG_SET			P83 = 1
    #define HDMI_HOTPLUG_CLEAR			P83 = 0
    #define HDMI_HOTPLUG_PINGET			g_p8_buf = P8
    #define HDMI_HOTPLUG_STATUS         (Bool)(g_p8_buf&0x08)
    #define HW_UPDATE_SET				P95 = 0
    #define HW_UPDATE_CLEAR				P95 = 1

#endif

/*******************************************************************
    define io for LCD250A board(LCD) here
*******************************************************************/
#elif defined(_CX32_LCD250A_ENABLE_)
#elif defined(_CX12_FB202A_ENABLE_)
#elif defined(_CX12_FB203B_ENABLE_)
#elif defined(_CX12_FB201A_ENABLE_)
#endif

#endif  //_IOCTRL_H_

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