tmem.c.svn-base

最新火热的ＣＸ３２ 源代码

/**
 * This file is about video chip register or FB data access                 
 * Application          : DPTV                                      
 * MCU                  : TMP91CU27UG-9999                              
 * Main Clock           : fc=27MHz                                      
 *                                                                      
 * Copyright (C) Trident Multimedia Technologies (Shanghai) Co., Ltd.   
 *                    2005  All rights reserved.                        
 * Revision:                                                            
 * 12/10/2005     Created by Lewis, Archie                              
 */

#include "tdefs.h"
#include "string.h"
#include "tdptv.h"

#define _USE_DMA_
//#undef _USE_DMA_

#ifdef _USE_DMA_

#if 0
void _far * memcpy(void _far *s1, const void _far *s2, size_t n)
{
    Byte ucVal; 
    tb0 = 20;   // Tested using 10MHz CPU CLK.  If you use faster CPU, may need to increase this value and test this function again.
    dm0con = 0x11;  // 8 bit, single transfer, forward->fixed
    sar0_addr.dword = (Dword)s2;
    dar0_addr.dword = (Dword)&ucVal;
    tcr0_addr.word = (Word)n - 1;
    dm1con = 0x21;  // 8 bit, single transfer, fixed->forward
    sar1_addr.dword = (Dword)&ucVal;
    dar1_addr.dword = (Dword)s1;
    tcr1_addr.word = (Word)n - 1;
    tb0s = _FALSE_;
    dm0con |= 0x08; // enable DMA0
    dm1con |= 0x08; // enable DMA1
    tb0s = _TRUE_;
    while (dm0con & 0x08);
    tb0 = 0;
    return ((Byte _far *)s1 + n);
}
#endif

#if 0
/* c -> DMA0 -> s, use TB0 as DMA request */
void _far * memset(void _far *s, int c, size_t n)
{
    /**
    dm0con = 0x21;  // 8 bit, single transfer, fixed->forward
    sar0_addr.dword = (Dword)&c;
    dar0_addr.dword = (Dword)s;
    tcr0_addr.word = n - 1;
    ta3ic = INT_PRIORITY_OFF;   //Disable timer3 interrupt, TTX line6 ISR will access reg
    dm0con |= 0x08; // enable DMA
    while (dm0con & 0x08);
    ta3ic = INT_PRIORITY_A;
    return s;
    **/
    __DMAM0 = 0x00;
    DMAB0 = 1;
    __DMAS0 = (Dword)&c;
    __DMAD0 = (Dword)s;
    __DMAC0 = n - 1;
    while(DMAR0|DMAR1|DMAR2|DMAR3) {}
    INTTA4 = INT_PRIORITY_OFF;                    //TimerA45
    INTTA5 = INT_PRIORITY_OFF;
    DMAR0 = 1;
    while (__DMAC0) {}
    while(DMAR0|DMAR1|DMAR2|DMAR3) {}
    INTTA4 = INT_PRIORITY_A;                    //TimerA45
    INTTA5 = INT_PRIORITY_A;
    DMAB0 = 0; 
    return s;
}
#endif
                       
void tdWritePortData(Byte ucPort, RPByte rpData, Word wSize)
{
    __DI();
    __DMAS0 = (Dword)rpData;
    __DMAD0 = (Dword)&DVADDRESS[ucPort];
    __DMAC0 = wSize;
    __DMAM0 = 0x08;
#ifdef USE_T_QUAD
    DMA0V = 0x00;
    DMAB = 0x01;
    DMAR = 0x01;
#else
    DMA0V = 0x15;
#endif
    __EI();
    while (__DMAC0) {;}
}

void tdReadPortData(Byte ucPort, APByte apData, Word wSize)
{
    __DI();
    __DMAM0 = 0x00;
    __DMAS0 = (Dword)&DVADDRESS[ucPort];
    __DMAD0 = (Dword)apData;
    __DMAC0 = wSize;
#ifdef USE_T_QUAD
    DMA0V = 0x00;
    DMAB = 0x01;
    DMAR = 0x01;
#else
    DMA0V = 0x15;
#endif
    __EI();
    while (__DMAC0) {;}
}

#else

Void tdWritePortData(Byte ucPort, RPByte rpData, Word wSize)
{
    tdInitDPTVWritePort(ucPort);
    while (wSize--)
        tdWriteDPTVPort(ucPort, *rpData++);
    tdTermDPTVWritePort();
}

Void tdReadPortData(Byte ucPort, APByte apData, Word wSize)
{
    tdInitDPTVReadPort(ucPort);
    while (wSize--)
        *apData++ = tdReadDPTVPort(ucPort);
    tdTermDPTVReadPort();
}

#endif