dmac_sample.c

oki67500系列arm工程例程源代码

            break;
        default:
            break;
    }
    put_wvalue(ILC0, 0x0);  /* disable all interrupts */
    put_wvalue(ILC1, 0x0);  /* disable all interrupts */
    
    irq_dis();  /* disable all interrupts */
    
    return(0);
}
/****************************************************************************/
/*  Setup of DMAC                                                           */
/*  Function : setup_dmac(UWORD,UWORD,UWORD,UWORD,UWORD)                    */
/*      Parameters                                                          */
/*          Input   : UWORD dmac_add    ... dmac channel base address       */
/*                          mode        ... dmac setting mode               */
/*                          s_add       ... source data start address       */
/*                          d_add       ... destination data start address  */
/*                          num_of_time ... number of time of transmit      */
/*          Output  : Nothing                                               */
/****************************************************************************/
void setup_dmac(UWORD dmac_add,UWORD mode,UWORD s_add,UWORD d_add,UWORD num_of_time)
{
    set_wbit((dmac_add + MSK),DMACMSK_MSK);     /* DMA stop  */
    
    put_wvalue((dmac_add + CINT),0x00ff);       /* end status clear */
    
    /* setup mode */
    put_wvalue((dmac_add + TMOD),mode);
    
    put_wvalue((dmac_add + SAD),s_add); /* set source data start address */
    
    put_wvalue((dmac_add + DAD),d_add); /* set destination data start address */
    
    put_wvalue((dmac_add + SIZ),num_of_time);   /* set the number of times 
                                                                of transmission */
    
    return;
}
/*****************************************************************************/
/*  DMAC CH0 interrupt handler                                               */
/*      Function : dmacCH0_handler(void)                                     */
/*          Parameters                                                       */
/*              Input  : Nothing                                             */
/*              Output : Nothing                                             */
/*****************************************************************************/
void dmacCH0_handler(void)
{
    UWORD sta = get_wvalue(DMAINT);
    
    set_wbit(DMACMSK0,DMACMSK_MSK); /* DMA CH0 stop */
    
    put_wvalue(DMACCINT0,0x00ff);   /* end status clear */
    
    if(sta & DMAINT_ISTA0){ /* error end ? */
        if(sta & DMAINT_ISTP0)  /* when did the error occur? */
            err_sta |= 0x04;   /* write cycle error */
        
        else
            err_sta |= 0x01;    /* read cycle error */
    }
    else
        ;
    
    ch0_flag = 1;
    
    return;
}
/*****************************************************************************/
/*  DMAC CH1 interrupt handler                                               */
/*      Function : dmacCH1_handler(void)                                     */
/*          Parameters                                                       */
/*              Input  : Nothing                                             */
/*              Output : Nothing                                             */
/*****************************************************************************/
void dmacCH1_handler(void)
{
    UWORD sta= get_wvalue(DMAINT);
    
    set_wbit(DMACMSK1,DMACMSK_MSK); /* DMA CH1 stop */
    put_wvalue(DMACCINT1,0x00ff);   /* end status clear */
    
    if(sta & DMAINT_ISTA1){     /* error end ? */
        if(sta & DMAINT_ISTP1)      /* when did the error occur? */
            err_sta |= 0x08;    /* write cycle error */
        
        else
            err_sta |= 0x02;    /* read cycle error */
    }
    else
        ;
    
    ch1_flag = 1;
    
    return;
}
/****************************************************************************/
/*  Registration of IRQ Handler                                             */
/*  Function : reg_irq_handler                                              */
/*      Parameters                                                          */
/*          Input   :   Nothing                                             */
/*          Output  :   Nothing                                             */
/*  Note : Initialize of IRQ needs to be performed before this process.     */
/****************************************************************************/
void reg_irq_handler(void)
{
    /* register IRQ handlers into handler table */
    IRQ_HANDLER_TABLE[INT_DMA0] = dmacCH0_handler;
    IRQ_HANDLER_TABLE[INT_DMA1] = dmacCH1_handler;
    
    /* setup interrupt level */
    set_wbit(ILC, ILC_ILC24 & ILC_INT_LV7);/* dma handler(nIRQ[24]) -> level7 */
    
    return;
}
/****************************************************************************/
/*  Setup of external DRAM                                                  */
/*  Function : setup_ext_dram                                               */
/*      Parameters                                                          */
/*          Input   :   Nothing                                             */
/*          Output  :   Nothing                                             */
/****************************************************************************/
void setup_ext_dram(void)
{
    int i;

    /* wait 200us (for HCLK:33MHz) */
    /* DBWC has to be set more than 200us after power was turned on. */
    /* please modify loop counts to suit your system. */
    for(i=0; i<0x530; i++)
        ;

    /* DRAM refresh cycle control register0,1 (RFSH0@0x7818_0014,RFSH1@0x7818_001C) */
    /* refresh cycle = 64KHz * 1 = 64KHz */
    put_wvalue(RFSH0, RFSH0_SINGLE);  /* magnification = 1 */
    put_wvalue(RFSH1, 0x0202);  /* cycle = 64KHz */

    /* DRAM bus width control register (DBWC@0x7818_0000) */
    put_wvalue(DBWC, DBWC_DBDRAM16);   /* bus width : 16bits */

    /* DRAM parameter control register (DRPC@0x7818_0008) */
    put_wvalue(DRPC, 0x9);

    /* all bank pre-charge */
    put_wvalue(DCMD, DCMD_S_PALL);

    /* CBR * 8 */
    for(i=0; i<8; i++)
        put_wvalue(DCMD, DCMD_S_REF);

    /* DRAM control register (DRMC@0x7818_0004) */
    put_wvalue(DRMC, DRMC_8bit|DRMC_SDRAM   /* AMUX:8bit, ARCH:SDRAM, */
                    |DRMC_2CLK|DRMC_PD_DIS  /* prelat:2clock, PDWN:disable, */
                    |DRMC_CBR_EXE);         /* CBR:execute */

    /* SDRAM mode register (SDMD@0x7818_000C) */
    put_wvalue(SDMD, SDMD_CL2|SDMD_MODEWR); /* CL-2
                                               only when MODEWR bit is written as 1,
                                               mode setup is performed. */

    /* DRAM power down mode control register (PDWC@0x7818_0018) */
    put_wvalue(PDWC, PDWC_16);  /* when 16 or more cycles of idol state continue,
                                   it shifts to power down mode.
                                   but automatic shifting to SDRAM power down mode
                                   is disable */

    return;
}