dmac_sample.c

oki67500系列arm工程例程源代码

/*************************************************************************************/
/*                                                                                   */
/*      Copyright (C) 2003 Oki Electric Industry Co., LTD.                           */
/*                                                                                   */
/*      System Name     :  ML675001 series                                           */
/*      Module Name     :  DMAC Sample Functions                                     */
/*      File   Name     :  dmac_sample.c                                             */
/*      Revision        :  1.00                                                      */
/*      Date            :  2003/08/18                                                */
/*                                                                                   */
/*************************************************************************************/
#include "ML675001.h"
#include "common.h"
#include "irq.h"
#include "cache.h"

/* DMAC channel base address */
#define DMAC_BASE0          0x7BE00100  /* DMAC CH0 base address */
#define DMAC_BASE1          0x7BE00200  /* DMAC CH1 base address */

/* DMAC channel registers (offset) */
#define MSK      0x0000     /* channel mask register */
#define TMOD     0x0004     /* transmit mode register */
#define SAD      0x0008     /* source data address register */
#define DAD      0x000c     /* destination data address register */
#define SIZ      0x0010     /* transmit size register */
#define CINT     0x0014     /* clear interrupt register */

/* setting channel */
#define CH0_MODE            0x003b  /* auto request, 16 bit transmission,
                                       source data type(incremental address device),
                                       destination data type(incremental address device),
                                       cycle steal mode,
                                       interrupt mask clear */
#define CH1_MODE            0x001b  /* auto request, 16 bit transmission,
                                       source data type(incremental address device),
                                       destination data type(incremental address device),
                                       burst mode,
                                       interrupt mask clear */

/* transmit start address */
#define CH0_S_START_ADD     0xC0000000  /* source data start address CH0 */
#define CH0_D_START_ADD     0xC0040000  /* destination data start address CH0 */
#define CH1_S_START_ADD     0xC0020000  /* source data start address CH1 */
#define CH1_D_START_ADD     0xC0060000  /* destination data start address CH1 */

/* the number of times of transmission */
#define NUM_OF_TIME_CH0     65536   /* the number of times of transmission CH0 */
#define NUM_OF_TIME_CH1     65536   /* the number of times of transmission CH1 */

/* LED lighting pattern */
#define READ_ERR_CH0        LED_1   /* read  cycle error CH0 */
#define READ_ERR_CH1        LED_2   /* read  cycle error CH1 */
#define WRITE_ERR_CH0       LED_3   /* write cycle error CH0 */
#define WRITE_ERR_CH1       LED_4   /* write cycle error CH1 */
#define RR_ERR_BOTH         LED_5   /* read  cycle error CH0 & read  cycle error CH1 */
#define WR_ERR_BOTH         LED_6   /* write cycle error CH0 & read  cycle error CH1 */
#define RW_ERR_BOTH         LED_7   /* read  cycle error CH0 & write cycle error CH1 */
#define WW_ERR_BOTH         LED_8   /* write cycle error CH0 & write cycle error CH1 */

/* functions */
int main(void);                                         /* main routine */
static void reg_irq_handler(void);                      /* registration of IRQ handler */
static void setup_dmac(UWORD,UWORD,UWORD,UWORD,UWORD);  /* setup Channel */
static void dmacCH0_handler(void);                      /* DMAC CH0 interrupt handler */
static void dmacCH1_handler(void);                      /* DMAC CH1 interrupt handler */
static void setup_ext_dram(void);                   /* setup external DRAM */
void led_on(UHWORD);                                    /* light LED */

/* global variables */
static volatile unsigned int ch0_flag;  /* end flag CH0(0: dma ch0 not end,
                                                        1: dma ch0 end) */
static volatile unsigned int ch1_flag;  /* end flag CH1(0: dma ch1 not end,
                                                        1: dma ch1 end) */
static volatile unsigned int err_sta;   /* error status(0x00: no error
                                        0x01: read  cycle error CH0,0x02: read  cycle error CH1,
                                        0x04: write cycle error CH0,0x08: write cycle error CH1,
                                        0x03: read  cycle error CH0 & read  cycle error CH1,
                                        0x06: write cycle error CH0 & read  cycle error CH1,
                                        0x09: read  cycle error CH0 & write cycle error CH1,
                                        0x0c: write cycle error CH0 & write cycle error CH1)*/

/****************************************************************************/
/*  Entry point                                                             */
/*  Function : main                                                         */
/*      Parameters                                                          */
/*          Input   :   Nothing                                             */
/*          Output  :   0                                                   */
/****************************************************************************/
int main(void)
{

    init_cache();  /* Initialize CACHE memory */
    cache_on(CACHE_BANK0);  /* Bank0 : Cache enable */

    /* initialize irq */
    init_irq();
    
    /* registration of IRQ handler */
    reg_irq_handler();
    
    /* initialize LED */
    init_led();   /* set output mode */
    
    led_on(LED_START_PATTERN);  /* light LED start pattern */
    
    /* selection of a secondary function */
    set_hbit(GPCTL,0x0008);     /* DMA CH0 */
    set_hbit(GPCTL,0x0010);     /* DMA CH1 */
    
    /* setup external DRAM */
    setup_ext_dram();

    /* initialize variables */
    ch0_flag = 0;
    ch1_flag = 0;
    err_sta  = 0x00;
    
    /* the order of priority */
    put_wvalue(DMAMOD,DMAMOD_FIX);  /* priority of DMA channel : CH0 > CH1 */
    
    /* setup DMAC CH0 */
    setup_dmac(DMAC_BASE0,CH0_MODE,CH0_S_START_ADD,CH0_D_START_ADD,NUM_OF_TIME_CH0);
    
    /* setup DMAC CH1 */
    setup_dmac(DMAC_BASE1,CH1_MODE,CH1_S_START_ADD,CH1_D_START_ADD,NUM_OF_TIME_CH1);
    
    /* enable IRQ */
    irq_en();
    
    /* DMA transmit start */
    clr_wbit(DMACMSK0,DMACMSK_MSK); /* CH0 start */
    clr_wbit(DMACMSK1,DMACMSK_MSK); /* CH1 start */
    
    while((ch0_flag == 0)||(ch1_flag == 0 ))  /* DMA transfer end ? */
        ;
    
    /* initialize function */
    clr_hbit(GPCTL,0x0008);     /* GPCTL bit3 selection of a primary function */
    clr_hbit(GPCTL,0x0010);     /* GPCTL bit4 selection of a primary function */
    
    /* end pattern */
    switch(err_sta){
        case (0x00):            /* normal end */
            led_on(LED_NORMAL_END_PATTERN);
            break;
        case (0x01):            /* CH0 read cycle error */
            led_on(READ_ERR_CH0);
            break;
        case (0x02):            /* CH1 read cycle error */
            led_on(READ_ERR_CH1);
            break;
        case (0x04):            /* CH0 write cycle error */
            led_on(WRITE_ERR_CH0);
            break;
        case (0x08):            /* CH1 write cycle error */
            led_on(WRITE_ERR_CH1);
            break;
        case (0x03):            /* CH0 read  cycle error & CH1 read  cycle error */
            led_on(RR_ERR_BOTH);
            break;
        case (0x06):            /* CH0 write cycle error & CH1 read  cycle error */
            led_on(WR_ERR_BOTH);
            break;
        case (0x09):            /* CH0 read  cycle error & CH1 write cycle error */
            led_on(RW_ERR_BOTH);
            break;
        case (0x0c):            /* CH0 write cycle error & CH1 write cycle error */
            led_on(WW_ERR_BOTH);