📄 cache_sample.c
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/**************************************************************************/
/* */
/* Copyright (C) 2003 Oki Electric Industry Co., LTD. */
/* */
/* System Name : ML675001 series */
/* Module Name : Cache sample program */
/* File Name : cache_sample.c */
/* Revision : 01.01 */
/* Date : 2003/08/18 */
/* */
/**************************************************************************/
#include "ML675001.h"
#include "common.h"
#include "cache.h"
#include "irq.h"
/* functions */
int main(void); /* main routine */
void write_back_test(void); /* write back test routine */
void write_back(void); /* write back routine */
void lock_test(void); /* lock test routine */
void dram_init(void); /* initialize ext.dram */
void sram_rom_init(void); /* initialize ext.sram/rom */
UWORD timer_measurement(void); /* measure data read time */
void data_read(UWORD address, UWORD size); /* dummy data read */
void reg_irq_handler(void); /* registration of IRQ handler */
void set_timer(void); /* setup TIMER */
void timer_handler(void); /* TIMER handler */
void lock(void);
/* global variables */
volatile UWORD timer_cnt; /* timer counter */
volatile UWORD lock_time1; /* lock test timer : time1 */
volatile UWORD lock_time2; /* lock test timer : time2 */
volatile UWORD lock_time3; /* lock test timer : time3 */
/******************************************************************/
/* Entry point */
/* Function : main */
/* Parameters */
/* Input : Nothing */
/* Output : 0 */
/******************************************************************/
int main(void)
{
init_led(); /* set output mode */
led_on(LED_START_PATTERN); /* Light LED start pattern */
init_irq(); /* initialize irq */
reg_irq_handler();
init_cache(); /* Initialize Cache */
dram_init(); /* setup external DRAM */
sram_rom_init();
write_back_test(); /* Write Back test */
irq_en(); /* enable irq */
lock_test(); /* Lock test */
irq_dis(); /* disable all interrupts */
led_on(LED_NORMAL_END_PATTERN); /* Light LED end LED_NORMAL_END_PATTERN */
return 0;
}
/****************************************************************************/
/* Initialize DRAM */
/* Function : dram_init */
/* Parameters */
/* Input : Nothing */
/* Output : Nothing */
/****************************************************************************/
void dram_init(void)
{
int i;
/* wait 200us (for HCLK:33MHz) */
/* DBWC has to be set more than 200us after power was turned on. */
/* please modify loop counts to suit your system. */
/* -- HCLK : 60MHz -- */
/* 2414 = 1328 * (60/33) */
/* 0x96E = */
for(i=0; i<0x96E; i++) {
}
/* DRAM refresh cycle control register0,1 (RFSH0@0x7818_0014,RFSH1@0x7818_001C) */
/* refresh cycle = 64KHz * 1 = 64KHz */
put_wvalue(RFSH0, RFSH0_SINGLE); /* magnification = 1 */
put_wvalue(RFSH1, 0x0202); /* cycle = 64KHz */
/* DRAM bus width control register (DBWC@0x7818_0000) */
put_wvalue(DBWC, DBWC_DBDRAM16); /* bus width : 16bits */
/* DRAM parameter control register (DRPC@0x7818_0008) */
put_wvalue(DRPC, 0x9);
/* all bank pre-charge */
put_wvalue(DCMD, DCMD_S_PALL);
/* CBR * 8 */
for(i=0; i<8; i++) {
put_wvalue(DCMD, DCMD_S_REF);
}
/* DRAM control register (DRMC@0x7818_0004) */
put_wvalue(DRMC, DRMC_8bit|DRMC_SDRAM /* AMUX:8bit, ARCH:SDRAM, */
|DRMC_2CLK|DRMC_PD_DIS /* prelat:2clock, PDWN:disable, */
|DRMC_CBR_EXE); /* CBR:execute */
/* SDRAM mode register (SDMD@0x7818_000C) */
put_wvalue(SDMD, SDMD_CL2|SDMD_MODEWR); /* CL-2
only when MODEWR bit is written as 1,
mode setup is performed. */
/* DRAM power down mode control register (PDWC@0x7818_0018) */
put_wvalue(PDWC, PDWC_16); /* when 16 or more cycles of idol state continue,
it shifts to power down mode.
but automatic shifting to SDRAM power down mode
is disable */
return;
}
/****************************************************************************/
/* Setup of external SRAM/ROM */
/* Function : sram_rom_init */
/* Parameters */
/* Input : Nothing */
/* Output : Nothing */
/****************************************************************************/
void sram_rom_init(void)
{
/* setup of bus width control register (BWC@0x7810_0000) */
put_wvalue(BWC, 0x28); /* setup of bus width
ROM/SRAM : 16bits.
IO0/IO1 : nothing */
/* setup of ROM access control register (ROMAC@0x7810_0004) */
put_wvalue(ROMAC, 0x7); /* OE/WE pulse width:8, read off time:4 (slowest) */
/* setup of SRAM access control register (RAMAC@0x7810_0008) */
put_wvalue(RAMAC, 0x7); /* OE/WE pulse width:8, read off time:4 (slowest) */
return;
}
/******************************************************************/
/* Write Back test */
/* Function : write_back_test */
/* Parameters */
/* Input : Nothing */
/* Output : Nothing */
/******************************************************************/
void write_back_test()
{
int address;
/* Clean ext.DRAM */
for(address = 0xC0002000; address < 0xC0004000; address++){
put_value(address, 0x00);
}
cache_on(CACHE_BANK24); /* ext.DRAM : Cache enable */
/* Set '0xFF'data to ext.DRAM */
for(address = 0xC0002000; address < 0xC0004000; address++){
put_value(address, 0xFF);
}
write_back();
cache_off(CACHE_BANK24); /* ext.DRAM : Cache disable */
return;
}
/******************************************************************/
/* Lock test */
/* Function : lock_test */
/* Parameters */
/* Input : Nothing */
/* Output : Nothing */
/******************************************************************/
void lock_test()
{
init_cache();
cache_on(CACHE_BANK24); /* DRAM BANK : Cache enable */
lock_time1 = timer_measurement(); /* Read Time is measured. */
lock_time2 = timer_measurement(); /* Read Time is measured. */
lock();
data_read(0xC0000000, 0x2000); /* Dummy data read (8Kbyte read) */
lock_time3 = timer_measurement(); /* Read Time is measured. */
return;
}
/******************************************************************/
/* Lock */
/* Function : lock */
/* Parameters */
/* Input : Nothing */
/* Output : Nothing */
/******************************************************************/
void lock(void)
{
write_back();
put_wvalue(CON, CON_WAY0 | CON_LOAD | CON_LOCK0); /* Set Load mode to Way0 */
data_read(0xC0004000, 0x800); /* dummy data read (2Kbytes) */
put_wvalue(CON, CON_LOCK1); /* One Way locke */
return;
}
/******************************************************************/
/* timer measurement */
/* Function : timer_measurement */
/* Parameters */
/* Input : Nothing */
/* Output : Nothing */
/******************************************************************/
UWORD timer_measurement(void)
{
UWORD ret_time,time0;
/* Initialize timer */
set_timer();
timer_cnt = 0;
/* timer start */
set_hbit(TIMECNTL0, TIMECNTL_START); /* TIMER0 */
data_read(0xC0004000, 0x2000); /* Dummy data read (8Kbyte read) */
/* stop timer */
clr_hbit(TIMECNTL0, TIMECNTL_START); /* TIMER0 */
time0 = get_hvalue(TIMECNT0);
ret_time = timer_cnt*0x10000+time0;
return ret_time;
}
/****************************************************************************/
/* Setup of timer */
/* Function : set_timer */
/* Parameters */
/* Input : Nothing */
/* Output : Nothing */
/****************************************************************************/
void set_timer(void)
{
/* stop timer */
put_hvalue(TIMECNTL0, 0); /* TIMER0 */
/* clear timer status register */
put_hvalue(TIMESTAT0, TIMESTAT_STATUS); /* TIMER0 */
/* setup timer control register */
put_hvalue(TIMECNTL0, /* TIMER0 */
TIMECNTL_CLK16 /* clock of timer = CCLK/16 */
|TIMECNTL_IE /* enable interrupt */
|TIMECNTL_INT); /* interval timer */
/* setup timer base register */
put_hvalue(TIMEBASE0, 0x0000); /* TIMER0 */
/* setup timer compare register */
put_hvalue(TIMECMP0, 0xFFFF); /* TIMER0 */
return;
}
/****************************************************************************/
/* Timer handler */
/* Function : timer_handler */
/* Parameters */
/* Input : Nothing */
/* Output : Nothing */
/****************************************************************************/
void timer_handler(void)
{
put_hvalue(TIMESTAT0, TIMESTAT_STATUS); /* clear timer status register */
timer_cnt++;
return;
}
/**********************************************************************/
/* Registration of IRQ Handler */
/* Function : reg_irq_handler */
/* Parameters */
/* Input : Nothing */
/* Output : Nothing */
/**********************************************************************/
void reg_irq_handler(void)
{
IRQ_HANDLER_TABLE[INT_TIMER0] = timer_handler; /* TIMER0 */
set_wbit(ILC, ILC_ILC16 & ILC_INT_LV3); /* timer0(nIR[16]) -> 3 */
return;
}
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