cache_asm.s

oki67500系列arm工程例程源代码

;/***************************************************************************************/
;/*                                                                                     */
;/*     Copyright (C) 2003 Oki Electric Industry Co., LTD.                              */
;/*                                                                                     */
;/*     System Name  :  ML675001 series                                                 */
;/*     Module Name  :  Cache sample program asm routine                                */
;/*     File   Name  :  cache_asm.s                                                     */
;/*     Revision     :  01.00                                                           */
;/*     Date         :  2003/08/18                                                      */
;/*                                                                                     */
;/***************************************************************************************/

        INCLUDE define.s

CON_WAY0        EQU     0x00000000      ; select Way0 (LCK bits) */
CON_WAY1        EQU     0x10000000      ; select Way1 (LCK bits) */
CON_WAY2        EQU     0x20000000      ; select Way2 (LCK bits) */
CON_WAY3        EQU     0x30000000      ; select Way3 (LCK bits) */
CON_LOAD        EQU     0x08000000      ; Load mode (F bit) */
CON_LOCK0       EQU     0x00000000      ; lock 0 Way (BNK bits) */
CON_LOCK1       EQU     0x02000000      ; lock 1 Way (BNK bits) */
CON_LOCK2       EQU     0x04000000      ; lock 2 Ways (BNK bits) */
CON_LOCK3       EQU     0x06000000      ; lock 3 Ways (BNK bits) */

WRITE_BACK_DUMMY        EQU     0xD8000000; mirror of ext.DRAM
        
        AREA    Asm_code, CODE, READONLY

;/***************************************************************************************/
;/*  data read                                                                          */
;/*  Function : data_read                                                               */
;/*      Parameters                                                                     */
;/*          Input  :  r0 - start address (multiple of 16bytes)                         */
;/*                    r1 - Read data size (multiple of 16bytes)                        */
;/*          Output :  Nothing                                                          */
;/*                                                                                     */
;/*  C API name : void data_read(UWORD *address, UWORD size)                            */
;/*      Parameters                                                                     */
;/*          Input  :  address - start address                                          */
;/*                    size - Read data size                                            */
;/*          Output :  Nothing                                                          */
;/***************************************************************************************/
        EXPORT  data_read
data_read
        ADD     r1, r0, r1
data_read_loop
        CMP     r0, r1
        LDMLOIA r0!, {r2-r3}    ; 16byte(=block size of cache memory) load
        LDMLOIA r0!, {r2-r3}    ; 
        BLO     data_read_loop
        BX      lr


;/***************************************************************************************/
;/*  write back                                                                         */
;/*  Function : write_back                                                              */
;/*      Parameters                                                                     */
;/*          Input  :  Nothing                                                          */
;/*          Output :  Nothing                                                          */
;/*                                                                                     */
;/*  C API name : void write_back(void)                                                 */
;/*      Parameters                                                                     */
;/*          Input  :  Nothing                                                          */
;/*          Output :  Nothing                                                          */
;/***************************************************************************************/
        EXPORT  write_back
write_back
        MOV     r12, lr         ; save lr
        LDR     r0, =WRITE_BACK_DUMMY
        LDR     r1, =0x78200000
        LDR     r2, [r1, #0x08]
        ORR     r2, r2, #0x00000800
        STR     r2, [r1, #0x08] ; set the bank27(mirror of ext.DRAM) cacheable
        MOV     r2, #CON_WAY0:OR:CON_LOAD:OR:CON_LOCK0
        BL      write_back_way
        MOV     r2, #CON_WAY1:OR:CON_LOAD:OR:CON_LOCK0
        BL      write_back_way
        MOV     r2, #CON_WAY2:OR:CON_LOAD:OR:CON_LOCK0
        BL      write_back_way
        MOV     r2, #CON_WAY3:OR:CON_LOAD:OR:CON_LOCK0
        BL      write_back_way
        LDR     r2, [r1, #0x08]
        BIC     r2, r2, #0x00000800
        STR     r2, [r1, #0x08] ; set the bank26(ext.SRAM) non-cacheable
        STR     r2, [r1, #0x1C] ; carry out a flushing operation of the cache memory
        BX      r12             ; return


;/******************************************************************************************/
;/*  write back 1way(2Kbyte) (sub function of write_back)                                  */
;/*  Function : write_back_way                                                             */
;/*      Parameters                                                                        */
;/*          Input  :  r0 - start address                                                  */
;/*                    r1 - base address of CACHE registers                                */
;/*                    r2 - setting value to CON register                                  */
;/*          Output :  r0 - end address + 1                                                */
;/*                    r1 - base address of CACHE registers                                */
;/******************************************************************************************/
write_back_way
        ADD     r3, r0, #0x800
        STR     r2, [r1, #4]    ; CON@0x78200004
write_back_way_loop
        CMP     r0, r3
        LDRLO   r2, [r0], #16
        BLO     write_back_way_loop
        MOV     pc, lr

        END