ym4_1.tan.qmsg

7段数码是纯组合电路

{ "Info" "ITDB_TSU_RESULT" "ledout\[5\]\$latch ledin\[0\] ledin\[1\] 4.481 ns register " "Info: tsu for register \"ledout\[5\]\$latch\" (data pin = \"ledin\[0\]\", clock pin = \"ledin\[1\]\") is 4.481 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.653 ns + Longest pin register " "Info: + Longest pin to register delay is 11.653 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ledin\[0\] 1 PIN PIN_100 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_100; Fanout = 7; PIN Node = 'ledin\[0\]'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledin[0] } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.856 ns) + CELL(0.114 ns) 8.439 ns Mux5~9 2 COMB LC_X5_Y10_N6 1 " "Info: 2: + IC(6.856 ns) + CELL(0.114 ns) = 8.439 ns; Loc. = LC_X5_Y10_N6; Fanout = 1; COMB Node = 'Mux5~9'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "6.970 ns" { ledin[0] Mux5~9 } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.624 ns) + CELL(0.590 ns) 11.653 ns ledout\[5\]\$latch 3 REG LC_X20_Y13_N2 1 " "Info: 3: + IC(2.624 ns) + CELL(0.590 ns) = 11.653 ns; Loc. = LC_X20_Y13_N2; Fanout = 1; REG Node = 'ledout\[5\]\$latch'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.214 ns" { Mux5~9 ledout[5]$latch } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.173 ns ( 18.65 % ) " "Info: Total cell delay = 2.173 ns ( 18.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.480 ns ( 81.35 % ) " "Info: Total interconnect delay = 9.480 ns ( 81.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "11.653 ns" { ledin[0] Mux5~9 ledout[5]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "11.653 ns" { ledin[0] ledin[0]~out0 Mux5~9 ledout[5]$latch } { 0.000ns 0.000ns 6.856ns 2.624ns } { 0.000ns 1.469ns 0.114ns 0.590ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.842 ns + " "Info: + Micro setup delay of destination is 0.842 ns" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ledin\[1\] destination 8.014 ns - Shortest register " "Info: - Shortest clock path from clock \"ledin\[1\]\" to destination register is 8.014 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ledin\[1\] 1 CLK PIN_10 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_10; Fanout = 8; CLK Node = 'ledin\[1\]'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledin[1] } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.493 ns) + CELL(0.114 ns) 3.076 ns Mux7~14 2 COMB LC_X5_Y10_N8 7 " "Info: 2: + IC(1.493 ns) + CELL(0.114 ns) = 3.076 ns; Loc. = LC_X5_Y10_N8; Fanout = 7; COMB Node = 'Mux7~14'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.607 ns" { ledin[1] Mux7~14 } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.824 ns) + CELL(0.114 ns) 8.014 ns ledout\[5\]\$latch 3 REG LC_X20_Y13_N2 1 " "Info: 3: + IC(4.824 ns) + CELL(0.114 ns) = 8.014 ns; Loc. = LC_X20_Y13_N2; Fanout = 1; REG Node = 'ledout\[5\]\$latch'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.938 ns" { Mux7~14 ledout[5]$latch } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.697 ns ( 21.18 % ) " "Info: Total cell delay = 1.697 ns ( 21.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.317 ns ( 78.82 % ) " "Info: Total interconnect delay = 6.317 ns ( 78.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "8.014 ns" { ledin[1] Mux7~14 ledout[5]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "8.014 ns" { ledin[1] ledin[1]~out0 Mux7~14 ledout[5]$latch } { 0.000ns 0.000ns 1.493ns 4.824ns } { 0.000ns 1.469ns 0.114ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "11.653 ns" { ledin[0] Mux5~9 ledout[5]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "11.653 ns" { ledin[0] ledin[0]~out0 Mux5~9 ledout[5]$latch } { 0.000ns 0.000ns 6.856ns 2.624ns } { 0.000ns 1.469ns 0.114ns 0.590ns } "" } } { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "8.014 ns" { ledin[1] Mux7~14 ledout[5]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "8.014 ns" { ledin[1] ledin[1]~out0 Mux7~14 ledout[5]$latch } { 0.000ns 0.000ns 1.493ns 4.824ns } { 0.000ns 1.469ns 0.114ns 0.114ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "ledin\[2\] ledout\[2\] ledout\[2\]\$latch 13.499 ns register " "Info: tco from clock \"ledin\[2\]\" to destination pin \"ledout\[2\]\" through register \"ledout\[2\]\$latch\" is 13.499 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ledin\[2\] source 8.264 ns + Longest register " "Info: + Longest clock path from clock \"ledin\[2\]\" to source register is 8.264 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ledin\[2\] 1 CLK PIN_7 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_7; Fanout = 8; CLK Node = 'ledin\[2\]'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledin[2] } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.588 ns) + CELL(0.292 ns) 3.349 ns Mux7~14 2 COMB LC_X5_Y10_N8 7 " "Info: 2: + IC(1.588 ns) + CELL(0.292 ns) = 3.349 ns; Loc. = LC_X5_Y10_N8; Fanout = 7; COMB Node = 'Mux7~14'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.880 ns" { ledin[2] Mux7~14 } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.801 ns) + CELL(0.114 ns) 8.264 ns ledout\[2\]\$latch 3 REG LC_X6_Y9_N2 1 " "Info: 3: + IC(4.801 ns) + CELL(0.114 ns) = 8.264 ns; Loc. = LC_X6_Y9_N2; Fanout = 1; REG Node = 'ledout\[2\]\$latch'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.915 ns" { Mux7~14 ledout[2]$latch } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.875 ns ( 22.69 % ) " "Info: Total cell delay = 1.875 ns ( 22.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.389 ns ( 77.31 % ) " "Info: Total interconnect delay = 6.389 ns ( 77.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "8.264 ns" { ledin[2] Mux7~14 ledout[2]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "8.264 ns" { ledin[2] ledin[2]~out0 Mux7~14 ledout[2]$latch } { 0.000ns 0.000ns 1.588ns 4.801ns } { 0.000ns 1.469ns 0.292ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.235 ns + Longest register pin " "Info: + Longest register to pin delay is 5.235 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ledout\[2\]\$latch 1 REG LC_X6_Y9_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y9_N2; Fanout = 1; REG Node = 'ledout\[2\]\$latch'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledout[2]$latch } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.111 ns) + CELL(2.124 ns) 5.235 ns ledout\[2\] 2 PIN PIN_98 0 " "Info: 2: + IC(3.111 ns) + CELL(2.124 ns) = 5.235 ns; Loc. = PIN_98; Fanout = 0; PIN Node = 'ledout\[2\]'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.235 ns" { ledout[2]$latch ledout[2] } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 40.57 % ) " "Info: Total cell delay = 2.124 ns ( 40.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.111 ns ( 59.43 % ) " "Info: Total interconnect delay = 3.111 ns ( 59.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.235 ns" { ledout[2]$latch ledout[2] } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "5.235 ns" { ledout[2]$latch ledout[2] } { 0.000ns 3.111ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "8.264 ns" { ledin[2] Mux7~14 ledout[2]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "8.264 ns" { ledin[2] ledin[2]~out0 Mux7~14 ledout[2]$latch } { 0.000ns 0.000ns 1.588ns 4.801ns } { 0.000ns 1.469ns 0.292ns 0.114ns } "" } } { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "5.235 ns" { ledout[2]$latch ledout[2] } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "5.235 ns" { ledout[2]$latch ledout[2] } { 0.000ns 3.111ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "ledout\[0\]\$latch ledin\[3\] ledin\[2\] 4.360 ns register " "Info: th for register \"ledout\[0\]\$latch\" (data pin = \"ledin\[3\]\", clock pin = \"ledin\[2\]\") is 4.360 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ledin\[2\] destination 8.289 ns + Longest register " "Info: + Longest clock path from clock \"ledin\[2\]\" to destination register is 8.289 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ledin\[2\] 1 CLK PIN_7 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_7; Fanout = 8; CLK Node = 'ledin\[2\]'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledin[2] } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.588 ns) + CELL(0.292 ns) 3.349 ns Mux7~14 2 COMB LC_X5_Y10_N8 7 " "Info: 2: + IC(1.588 ns) + CELL(0.292 ns) = 3.349 ns; Loc. = LC_X5_Y10_N8; Fanout = 7; COMB Node = 'Mux7~14'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.880 ns" { ledin[2] Mux7~14 } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.826 ns) + CELL(0.114 ns) 8.289 ns ledout\[0\]\$latch 3 REG LC_X5_Y10_N5 1 " "Info: 3: + IC(4.826 ns) + CELL(0.114 ns) = 8.289 ns; Loc. = LC_X5_Y10_N5; Fanout = 1; REG Node = 'ledout\[0\]\$latch'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "4.940 ns" { Mux7~14 ledout[0]$latch } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.875 ns ( 22.62 % ) " "Info: Total cell delay = 1.875 ns ( 22.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.414 ns ( 77.38 % ) " "Info: Total interconnect delay = 6.414 ns ( 77.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "8.289 ns" { ledin[2] Mux7~14 ledout[0]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "8.289 ns" { ledin[2] ledin[2]~out0 Mux7~14 ledout[0]$latch } { 0.000ns 0.000ns 1.588ns 4.826ns } { 0.000ns 1.469ns 0.292ns 0.114ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.929 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.929 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ledin\[3\] 1 CLK PIN_16 6 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 6; CLK Node = 'ledin\[3\]'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { ledin[3] } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.437 ns) + CELL(0.292 ns) 3.198 ns Mux0~9 2 COMB LC_X5_Y10_N2 1 " "Info: 2: + IC(1.437 ns) + CELL(0.292 ns) = 3.198 ns; Loc. = LC_X5_Y10_N2; Fanout = 1; COMB Node = 'Mux0~9'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.729 ns" { ledin[3] Mux0~9 } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.439 ns) + CELL(0.292 ns) 3.929 ns ledout\[0\]\$latch 3 REG LC_X5_Y10_N5 1 " "Info: 3: + IC(0.439 ns) + CELL(0.292 ns) = 3.929 ns; Loc. = LC_X5_Y10_N5; Fanout = 1; REG Node = 'ledout\[0\]\$latch'" {  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.731 ns" { Mux0~9 ledout[0]$latch } "NODE_NAME" } } { "ym4_1.vhd" "" { Text "E:/20044693/ym4_1.vhd" 8 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.053 ns ( 52.25 % ) " "Info: Total cell delay = 2.053 ns ( 52.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.876 ns ( 47.75 % ) " "Info: Total interconnect delay = 1.876 ns ( 47.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.929 ns" { ledin[3] Mux0~9 ledout[0]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "3.929 ns" { ledin[3] ledin[3]~out0 Mux0~9 ledout[0]$latch } { 0.000ns 0.000ns 1.437ns 0.439ns } { 0.000ns 1.469ns 0.292ns 0.292ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "8.289 ns" { ledin[2] Mux7~14 ledout[0]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "8.289 ns" { ledin[2] ledin[2]~out0 Mux7~14 ledout[0]$latch } { 0.000ns 0.000ns 1.588ns 4.826ns } { 0.000ns 1.469ns 0.292ns 0.114ns } "" } } { "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/eda_tool/altera7.1/quartus/bin/TimingClosureFloorplan.fld" "" "3.929 ns" { ledin[3] Mux0~9 ledout[0]$latch } "NODE_NAME" } } { "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/eda_tool/altera7.1/quartus/bin/Technology_Viewer.qrui" "3.929 ns" { ledin[3] ledin[3]~out0 Mux0~9 ledout[0]$latch } { 0.000ns 0.000ns 1.437ns 0.439ns } { 0.000ns 1.469ns 0.292ns 0.292ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 10 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "106 " "Info: Allocated 106 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 03 16:30:27 2007 " "Info: Processing ended: Mon Dec 03 16:30:27 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}