📄 rccu.s79
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TST R1,#0x2
BEQ ??RCCU_RCLKSourceConfig_6
// 77 /* Deselect The CKAF */
// 78 RCCU->CCR &= ~RCCU_CKAF_SEL_Mask;
??RCCU_RCLKSourceConfig_5:
MOV R1,#-1610612736
MOV R2,#-1610612736
LDR R2,[R2, #+0]
BICS R2,R2,#0x4
STR R2,[R1, #+0]
// 79 /* Select The CSU_CKSEL */
// 80 RCCU->CFR |= RCCU_CSU_CKSEL_Mask;
MOV R1,#-1610612728
MOV R2,#-1610612728
LDR R2,[R2, #+0]
ORRS R2,R2,#0x1
STR R2,[R1, #+0]
// 81 break;}
B ??RCCU_RCLKSourceConfig_1
// 82 case RCCU_RTC_CLOCK : {RCCU->CCR |= 0x04;
??RCCU_RCLKSourceConfig_7:
MOV R1,#-1610612736
MOV R2,#-1610612736
LDR R2,[R2, #+0]
ORRS R2,R2,#0x4
STR R2,[R1, #+0]
// 83 break;}
// 84 }
// 85 }
??RCCU_RCLKSourceConfig_1:
MOV PC,LR ;; return
CFI EndBlock cfiBlock2
// 86
// 87 /*******************************************************************************
// 88 * Function Name : RCCU_RCLKClockSource
// 89 * Description : Returns the current RCLK source clock
// 90 * Input : None
// 91 * Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2, RCCU_RTC_CLOCK
// 92 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock3 Using cfiCommon0
CFI Function RCCU_RCLKClockSource
ARM
// 93 RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void )
// 94 {
// 95 if ((RCCU->CCR & 0x04)==0x04)
RCCU_RCLKClockSource:
MOV R0,#-1610612736
LDR R0,[R0, #+0]
TST R0,#0x4
BEQ ??RCCU_RCLKClockSource_0
// 96 return RCCU_RTC_CLOCK;
MOV R0,#+3
B ??RCCU_RCLKClockSource_1
// 97
// 98 else if ((RCCU->CFR & RCCU_CK2_16_Mask)==0)
??RCCU_RCLKClockSource_0:
MOV R0,#-1610612728
LDR R0,[R0, #+0]
TST R0,#0x8
BNE ??RCCU_RCLKClockSource_2
// 99 return RCCU_CLOCK2_16;
MOV R0,#+1
B ??RCCU_RCLKClockSource_1
// 100
// 101 else if (RCCU->CFR & RCCU_CSU_CKSEL_Mask)
??RCCU_RCLKClockSource_2:
MOV R0,#-1610612728
LDR R0,[R0, #+0]
TST R0,#0x1
BEQ ??RCCU_RCLKClockSource_3
// 102 return RCCU_PLL1_Output;
MOV R0,#+0
B ??RCCU_RCLKClockSource_1
// 103
// 104 else
// 105 return RCCU_CLOCK2;
??RCCU_RCLKClockSource_3:
MOV R0,#+2
??RCCU_RCLKClockSource_1:
MOV PC,LR ;; return
CFI EndBlock cfiBlock3
// 106 }
// 107
// 108 /*******************************************************************************
// 109 * Function Name : RCCU_FrequencyValue
// 110 * Description : Calculates & Returns any internal RCCU clock frequency
// 111 * passed in parametres
// 112 * Input : RCCU_Clocks ( RCCU_CLK2, RCCU_RCLK, RCCU_MCLK, RCCU_PCLK, RCCU_FCLK )
// 113 * Return : u32
// 114 *******************************************************************************/
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock4 Using cfiCommon0
CFI Function RCCU_FrequencyValue
ARM
// 115 u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk )
// 116 {
RCCU_FrequencyValue:
PUSH {R4-R8,LR}
CFI ?RET Frame(CFA, -4)
CFI R8 Frame(CFA, -8)
CFI R7 Frame(CFA, -12)
CFI R6 Frame(CFA, -16)
CFI R5 Frame(CFA, -20)
CFI R4 Frame(CFA, -24)
CFI CFA R13+24
MOVS R4,R0
// 117 u32 Tmp;
// 118 u8 Div = 0;
MOV R0,#+0
MOVS R5,R0
// 119 u8 Mul = 0;
MOV R0,#+0
MOVS R6,R0
// 120 RCCU_RCLK_Clocks CurrentRCLK;
// 121
// 122 Tmp = ( RCCU_Div2Status() == SET )? RCCU_Main_Osc / 2 : RCCU_Main_Osc;
_BLF RCCU_Div2Status,??RCCU_Div2Status??rA
CMP R0,#+1
BNE ??RCCU_FrequencyValue_3
MOV R8,#+7995392
ORR R8,R8,#0x1200
B ??RCCU_FrequencyValue_4
??RCCU_FrequencyValue_3:
MOV R8,#+15990784
ORR R8,R8,#0x2400
// 123
// 124 if ( Internal_Clk == RCCU_CLK2 )
??RCCU_FrequencyValue_4:
CMP R4,#+0
BNE ??RCCU_FrequencyValue_5
// 125 {
// 126 Div = 1;
MOV R0,#+1
MOVS R5,R0
// 127 Mul = 1;
MOV R0,#+1
MOVS R6,R0
B ??RCCU_FrequencyValue_6
// 128 }
// 129 else
// 130 { CurrentRCLK = RCCU_RCLKClockSource ();
??RCCU_FrequencyValue_5:
BL RCCU_RCLKClockSource
MOVS R7,R0
// 131 switch ( CurrentRCLK ){
MOVS R0,R7
CMP R0,#+3
BHI ??RCCU_FrequencyValue_6
ADR R1,??RCCU_FrequencyValue_0
LDRB R1,[R1, R0]
ADD PC,PC,R1, LSL #+2
DATA
??RCCU_FrequencyValue_0:
DC8 +10,+0,+5,+42
ARM
// 132 case RCCU_CLOCK2_16 : Div = 16;
??RCCU_FrequencyValue_7:
MOV R0,#+16
MOVS R5,R0
// 133 Mul = 1;
MOV R0,#+1
MOVS R6,R0
B ??RCCU_FrequencyValue_6
// 134 break;
// 135 case RCCU_CLOCK2 : Div = 1;
??RCCU_FrequencyValue_8:
MOV R0,#+1
MOVS R5,R0
// 136 Mul = 1;
MOV R0,#+1
MOVS R6,R0
B ??RCCU_FrequencyValue_6
// 137 break;
// 138 case RCCU_PLL1_Output :{Mul=(RCCU->PLL1CR & RCCU_MX_Mask ) >> RCCU_MX_Index;
??RCCU_FrequencyValue_9:
MOV R0,#+24
ORR R0,R0,#0xA0000000
LDR R0,[R0, #+0]
ANDS R0,R0,#0x30
LSRS R0,R0,#+4
MOVS R6,R0
// 139 switch ( Mul )
MOVS R0,R6
ANDS R0,R0,#0xFF ;; Zero extend
CMP R0,#+3
BHI ??RCCU_FrequencyValue_10
ADR R1,??RCCU_FrequencyValue_1
LDRB R1,[R1, R0]
ADD PC,PC,R1, LSL #+2
DATA
??RCCU_FrequencyValue_1:
DC8 +0,+3,+6,+9
ARM
// 140 {case 0: Mul = 20; break;
??RCCU_FrequencyValue_11:
MOV R0,#+20
MOVS R6,R0
B ??RCCU_FrequencyValue_10
// 141 case 1: Mul = 12; break;
??RCCU_FrequencyValue_12:
MOV R0,#+12
MOVS R6,R0
B ??RCCU_FrequencyValue_10
// 142 case 2: Mul = 28; break;
??RCCU_FrequencyValue_13:
MOV R0,#+28
MOVS R6,R0
B ??RCCU_FrequencyValue_10
// 143 case 3: Mul = 16; break;
??RCCU_FrequencyValue_14:
MOV R0,#+16
MOVS R6,R0
// 144 }
// 145 Div = ( RCCU->PLL1CR & RCCU_DX_Mask ) + 1;
??RCCU_FrequencyValue_10:
MOV R0,#+24
ORR R0,R0,#0xA0000000
LDR R0,[R0, #+0]
ANDS R0,R0,#0x7
ADDS R0,R0,#+1
MOVS R5,R0
// 146 break;}
B ??RCCU_FrequencyValue_6
// 147 case RCCU_RTC_CLOCK : Mul = 1;
??RCCU_FrequencyValue_15:
MOV R0,#+1
MOVS R6,R0
// 148 Div = 1;
MOV R0,#+1
MOVS R5,R0
// 149 Tmp = RCCU_RTC_Osc;
MOV R0,#+32768
MOVS R8,R0
// 150 break;}}
// 151
// 152 switch ( Internal_Clk ){
??RCCU_FrequencyValue_6:
MOVS R0,R4
SUB R0,R0,#+2
CMP R0,#+2
BHI ??RCCU_FrequencyValue_16
ADR R1,??RCCU_FrequencyValue_2
LDRB R1,[R1, R0]
ADD PC,PC,R1, LSL #+2
DATA
??RCCU_FrequencyValue_2:
DC8 +0,+6,+15,+0
ARM
// 153 case RCCU_MCLK :{Div <<= PCU->MDIVR & RCCU_FACT_Mask;
??RCCU_FrequencyValue_17:
MOV R0,#+64
ORR R0,R0,#0xA0000000
LDRH R0,[R0, #+0]
ANDS R0,R0,#0x3
LSLS R5,R5,R0
// 154 break;}
B ??RCCU_FrequencyValue_16
// 155 case RCCU_PCLK :{Div <<=(PCU->PDIVR & RCCU_FACT2_Mask ) >> RCCU_FACT2_Index;
??RCCU_FrequencyValue_18:
MOV R0,#+68
ORR R0,R0,#0xA0000000
LDRH R0,[R0, #+0]
MOV R0,R0, LSL #+16
MOVS R0,R0, LSR #+16
ANDS R0,R0,#0x300
ASRS R0,R0,#+8
LSLS R5,R5,R0
// 156 break;}
B ??RCCU_FrequencyValue_16
// 157 case RCCU_FCLK :{Div <<= PCU->PDIVR & 0x3;
??RCCU_FrequencyValue_19:
MOV R0,#+68
ORR R0,R0,#0xA0000000
LDRH R0,[R0, #+0]
ANDS R0,R0,#0x3
LSLS R5,R5,R0
// 158 break;}}
// 159
// 160 return (Tmp * Mul) / Div;
??RCCU_FrequencyValue_16:
ANDS R6,R6,#0xFF ;; Zero extend
MULS R0,R6,R8
ANDS R5,R5,#0xFF ;; Zero extend
MOVS R1,R5
_BLF ??divu32_a,??rA??divu32_a
MOVS R0,R1
POP {R4-R8,PC} ;; return
CFI EndBlock cfiBlock4
// 161 }
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock5 Using cfiCommon0
CFI NoFunction
ARM
??RCCU_Div2Status??rA:
LDR R12,??Subroutine0_0 ;; RCCU_Div2Status
MOV PC,R12
DATA
??Subroutine0_0:
DC32 RCCU_Div2Status
CFI EndBlock cfiBlock5
RSEG CODE:CODE:NOROOT(2)
CFI Block cfiBlock6 Using cfiCommon0
CFI NoFunction
ARM
??rA??divu32_a:
LDR R12,??Subroutine1_0 ;; ??divu32_a
MOV PC,R12
DATA
??Subroutine1_0:
DC32 ??divu32_a
CFI EndBlock cfiBlock6
END
// 162
// 163 /******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/
//
// 1 080 bytes in segment CODE
//
// 1 024 bytes of CODE memory (+ 56 bytes shared)
//
//Errors: none
//Warnings: none
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